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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h126 #define CHIP_MIIC1_PAD_1 (__BIT2)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
143 #define CHIP_REG_HWI2C_MIIC0_CLK_XTAL (__BIT2)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
171 #define _MIIC_CFG_EN_INT (__BIT2)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
195 #define _INT_RXDONE (__BIT2)
207 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h126 #define CHIP_MIIC1_PAD_1 (__BIT2)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
143 #define CHIP_REG_HWI2C_MIIC0_CLK_XTAL (__BIT2)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
171 #define _MIIC_CFG_EN_INT (__BIT2)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
195 #define _INT_RXDONE (__BIT2)
207 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h126 #define CHIP_MIIC1_PAD_1 (__BIT2)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
143 #define CHIP_REG_HWI2C_MIIC0_CLK_XTAL (__BIT2)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
171 #define _MIIC_CFG_EN_INT (__BIT2)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
195 #define _INT_RXDONE (__BIT2)
207 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h126 #define CHIP_MIIC1_PAD_1 (__BIT2)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
143 #define CHIP_REG_HWI2C_MIIC0_CLK_XTAL (__BIT2)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
171 #define _MIIC_CFG_EN_INT (__BIT2)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
195 #define _INT_RXDONE (__BIT2)
207 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h122 #define CHIP_MIIC1_PAD_1 (__BIT2)
124 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
142 #define CHIP_MIIC4_PAD_1 (__BIT2)
143 #define CHIP_MIIC4_PAD_MSK (__BIT2)
166 #define _MIIC_CFG_EN_INT (__BIT2)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
190 #define _INT_RXDONE (__BIT2)
202 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
208 #define _DMA_CFG_INTEN (__BIT2)
229 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h122 #define CHIP_MIIC1_PAD_1 (__BIT2)
124 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
142 #define CHIP_MIIC4_PAD_1 (__BIT2)
143 #define CHIP_MIIC4_PAD_MSK (__BIT2)
166 #define _MIIC_CFG_EN_INT (__BIT2)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
190 #define _INT_RXDONE (__BIT2)
202 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
208 #define _DMA_CFG_INTEN (__BIT2)
229 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
228 #define _DMA_CFG_INTEN (__BIT2)
250 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
257 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
228 #define _DMA_CFG_INTEN (__BIT2)
250 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
257 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
228 #define _DMA_CFG_INTEN (__BIT2)
250 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
257 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
139 #define CHIP_MIIC3_PAD_MSK (__BIT1|__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
228 #define _DMA_CFG_INTEN (__BIT2)
250 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
257 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
210 #define _DMA_CFG_INTEN (__BIT2)
231 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
238 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
210 #define _DMA_CFG_INTEN (__BIT2)
231 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
238 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
210 #define _DMA_CFG_INTEN (__BIT2)
231 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
238 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC2_PAD_1 (__BIT2)
128 #define CHIP_MIIC2_PAD_MSK (__BIT2)
168 #define _MIIC_CFG_EN_INT (__BIT2)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_RXDONE (__BIT2)
204 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
228 #define _DMA_CFG_INTEN (__BIT2)
250 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
257 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h146 #define _MIIC_CFG_EN_INT (__BIT2)
166 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
170 #define _INT_RXDONE (__BIT2)
182 #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0)
188 #define _DMA_CFG_INTEN (__BIT2)
209 #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0)
216 #define _DMA_10BIT_MODE (__BIT2)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h108 #define __BIT2 __BIT(2) macro
168 #define EMM_OVERFLOW_INT __BIT2
208 #define EMM_CLR_PVR_OVERFLOW __BIT2
218 #define EMM_FIRST_4_BYTES __BIT2
228 #define EMM_STR2MIU_RST_WADR __BIT2
252 #define REG_WADR_PROTECT_EN __BIT2
268 #define REG_SIM_C0_CONFIG __BIT2
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h108 #define __BIT2 __BIT(2) macro
168 #define EMM_OVERFLOW_INT __BIT2
208 #define EMM_CLR_PVR_OVERFLOW __BIT2
218 #define EMM_FIRST_4_BYTES __BIT2
228 #define EMM_STR2MIU_RST_WADR __BIT2
252 #define REG_WADR_PROTECT_EN __BIT2
268 #define REG_SIM_C0_CONFIG __BIT2
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h108 #define __BIT2 __BIT(2) macro
168 #define EMM_OVERFLOW_INT __BIT2
208 #define EMM_CLR_PVR_OVERFLOW __BIT2
218 #define EMM_FIRST_4_BYTES __BIT2
228 #define EMM_STR2MIU_RST_WADR __BIT2
252 #define REG_WADR_PROTECT_EN __BIT2
268 #define REG_SIM_C0_CONFIG __BIT2
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h108 #define __BIT2 __BIT(2) macro
168 #define EMM_OVERFLOW_INT __BIT2
208 #define EMM_CLR_PVR_OVERFLOW __BIT2
218 #define EMM_FIRST_4_BYTES __BIT2
228 #define EMM_STR2MIU_RST_WADR __BIT2
252 #define REG_WADR_PROTECT_EN __BIT2
268 #define REG_SIM_C0_CONFIG __BIT2
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h108 #define __BIT2 __BIT(2) macro
168 #define EMM_OVERFLOW_INT __BIT2
208 #define EMM_CLR_PVR_OVERFLOW __BIT2
218 #define EMM_FIRST_4_BYTES __BIT2
228 #define EMM_STR2MIU_RST_WADR __BIT2
252 #define REG_WADR_PROTECT_EN __BIT2
268 #define REG_SIM_C0_CONFIG __BIT2
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
607 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_SetSRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, ENABLE, __BIT2); //DRAM enable in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT2)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_Disable51()
756 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
605 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_SetSRAMOffsetForMCU()
653 HAL_PM_WriteRegBit(0x001018UL, ENABLE, __BIT2); //DRAM enable in HAL_PM_SetDRAMOffsetForMCU()
731 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT2)); in HAL_PM_Disable51()
736 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
605 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_SetSRAMOffsetForMCU()
653 HAL_PM_WriteRegBit(0x001018UL, ENABLE, __BIT2); //DRAM enable in HAL_PM_SetDRAMOffsetForMCU()
731 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT2)); in HAL_PM_Disable51()
736 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
605 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_SetSRAMOffsetForMCU()
653 HAL_PM_WriteRegBit(0x001018UL, ENABLE, __BIT2); //DRAM enable in HAL_PM_SetDRAMOffsetForMCU()
731 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT2)); in HAL_PM_Disable51()
736 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
605 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_SetSRAMOffsetForMCU()
653 HAL_PM_WriteRegBit(0x001018UL, ENABLE, __BIT2); //DRAM enable in HAL_PM_SetDRAMOffsetForMCU()
731 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT2)); in HAL_PM_Disable51()
736 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT2); //DRAM disable in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)

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