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Searched refs:UPDATE_DC1_FREERUN_CW (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/
H A DregMVOP.h407 #define UPDATE_DC1_FREERUN_CW BIT3 macro
H A DhalMVOP.c3849 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
3850 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DregMVOP.h427 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4633 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4634 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/
H A DregMVOP.h425 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/
H A DregMVOP.h418 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4364 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4365 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DregMVOP.h432 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/
H A DregMVOP.h425 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4770 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4771 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h448 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4485 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4486 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DregMVOP.h433 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4842 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4843 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h445 #define UPDATE_DC1_FREERUN_CW BIT0 macro
H A DhalMVOP.c4821 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4822 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/
H A DregMVOP.h437 #define UPDATE_DC1_FREERUN_CW BIT3 macro
H A DhalMVOP.c4355 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4356 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h460 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/
H A DregMVOP.h457 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/
H A DregMVOP.h458 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h465 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/
H A DregMVOP.h445 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h493 #define UPDATE_DC1_FREERUN_CW BIT0 macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h526 #define UPDATE_DC1_FREERUN_CW BIT0 macro

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