RIUBASE_IRQ_EXP (reference) in projects: utopia

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Searched refs:RIUBASE_IRQ_EXP (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/irq/hal/mainz/irq/
H A D	regIRQ.h	110 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 119 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0066 << 1)) 120 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x006E << 1)) 121 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x006E << 1)) 123 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0076 << 1)) 124 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x007E << 1)) 133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) 134 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x002E << 1)) 135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) 137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/mooney/irq/
H A D	regIRQ.h	110 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 119 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0066 << 1)) 120 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x006E << 1)) 121 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x006E << 1)) 123 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0076 << 1)) 124 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x007E << 1)) 133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) 134 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x002E << 1)) 135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) 137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/messi/irq/
H A D	regIRQ.h	110 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 119 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0066 << 1)) 120 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x006E << 1)) 121 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x006E << 1)) 123 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0076 << 1)) 124 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x007E << 1)) 133 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0026 << 1)) 134 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x002E << 1)) 135 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x002E << 1)) 137 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x0036 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/kano/irq/
H A D	regIRQ.h	111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/k7u/irq/
H A D	regIRQ.h	111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/k6lite/irq/
H A D	regIRQ.h	111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/curry/irq/
H A D	regIRQ.h	111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/k6/irq/
H A D	regIRQ.h	111 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 121 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x26 << 1)) 122 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2e << 1)) 123 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2e << 1)) 128 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x36 << 1)) 129 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3e << 1)) 141 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x46 << 1)) 142 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x4e << 1)) 143 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x4e << 1)) 148 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x56 << 1)) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/mustang/irq/
H A D	regIRQ.h	108 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 123 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x262)) //NOT EXIST NOW 124 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2E2)) //NOT EXIST NOW 125 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2E2)) //NOT EXIST NOW 127 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x362)) //NOT EXIST NOW 128 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3E2)) //NOT EXIST NOW 143 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x462) 144 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x4E2) 145 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x4E2) 147 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x56*2) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/maldives/irq/
H A D	regIRQ.h	108 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 123 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x262)) //NOT EXIST NOW 124 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x2E2)) //NOT EXIST NOW 125 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x2E2)) //NOT EXIST NOW 127 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x362)) //NOT EXIST NOW 128 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x3E2)) //NOT EXIST NOW 143 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x462) 144 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x4E2) 145 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x4E2) 147 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x56*2) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/maserati/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/manhattan/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/maxim/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/M7621/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) //[IRQ][HAL][004] Mask b… 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) //[IRQ][HAL][005] Clear … 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) //[IRQ][HAL][006] Status… 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) //[IRQ][HAL][009] Mask b… [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/M7821/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) //[IRQ][HAL][004] Mask b… 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) //[IRQ][HAL][005] Clear … 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) //[IRQ][HAL][006] Status… 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) //[IRQ][HAL][009] Mask b… [all …]
/utopia/UTPA2-700.0.x/modules/irq/hal/macan/irq/
H A D	regIRQ.h	107 #define RIUBASE_IRQ_EXP 0x1900 //(0x101900-0x100000) macro 154 #define REG_AEON_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x662)) //NOT EXIST NOW 155 #define REG_AEON_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x6E2)) //NOT EXIST NOW 162 #define REG_AEON_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + (0x762)) //NOT EXIST NOW 163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + (0x7E2)) //NOT EXIST NOW 181 #define REG_MIPS_C_FIQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x262) 182 #define REG_MIPS_C_FIQ_EXP_CLR (RIUBASE_IRQ_EXP + 0x2E2) 183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS (RIUBASE_IRQ_EXP + 0x2E2) 189 #define REG_MIPS_C_IRQ_EXP_MASK (RIUBASE_IRQ_EXP + 0x36*2) [all …]