Lines Matching refs:RIUBASE_IRQ_EXP

107 #define RIUBASE_IRQ_EXP     0x1900   //(0x101900-0x100000)  macro
154 #define REG_AEON_C_FIQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x66*2)) //NOT EXIST NOW
155 #define REG_AEON_C_FIQ_EXP_CLR                  (RIUBASE_IRQ_EXP + (0x6E*2)) //NOT EXIST NOW
156 #define REG_AEON_C_FIQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x6E*2)) //NOT EXIST NOW
162 #define REG_AEON_C_IRQ_EXP_MASK                 (RIUBASE_IRQ_EXP + (0x76*2)) //NOT EXIST NOW
163 #define REG_AEON_C_IRQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + (0x7E*2)) //NOT EXIST NOW
181 #define REG_MIPS_C_FIQ_EXP_MASK                 (RIUBASE_IRQ_EXP + 0x26*2)
182 #define REG_MIPS_C_FIQ_EXP_CLR                  (RIUBASE_IRQ_EXP + 0x2E*2)
183 #define REG_MIPS_C_FIQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + 0x2E*2)
189 #define REG_MIPS_C_IRQ_EXP_MASK                 (RIUBASE_IRQ_EXP + 0x36*2)
190 #define REG_MIPS_C_IRQ_EXP_FINAL_STATUS         (RIUBASE_IRQ_EXP + 0x3E*2)