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Searched refs:REG_VDR2_D_ACCESS_RANGE0_CFG (Results 1 – 6 of 6) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DhalVPU_EX.c1158 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1162 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1184 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1193 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1202 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1209 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_A… in _VPU_EX_InitAddressLimiter()
1214 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_A… in _VPU_EX_InitAddressLimiter()
H A DregVPU_EX.h488 #define REG_VDR2_D_ACCESS_RANGE0_CFG (BLK_CODEC_REG_BASE+(0x0020<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DhalVPU_EX.c1157 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1161 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1183 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1192 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1201 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1208 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_A… in _VPU_EX_InitAddressLimiter()
1213 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_A… in _VPU_EX_InitAddressLimiter()
H A DregVPU_EX.h488 #define REG_VDR2_D_ACCESS_RANGE0_CFG (BLK_CODEC_REG_BASE+(0x0020<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DhalVPU_EX.c1154 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_LOCK_RD_LAT_CLR, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1158 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ALWAYS_PASS_W_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1180 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_… in _VPU_EX_InitAddressLimiter()
1189 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_… in _VPU_EX_InitAddressLimiter()
1198 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2… in _VPU_EX_InitAddressLimiter()
1205 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_REF_ADDR0_RANGE_PASS_W_A… in _VPU_EX_InitAddressLimiter()
1210 …_VPU_WriteWordMask(REG_VDR2_D_ACCESS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_ADDR0_LIMIT_EN, VDR2_D_A… in _VPU_EX_InitAddressLimiter()
H A DregVPU_EX.h488 #define REG_VDR2_D_ACCESS_RANGE0_CFG (BLK_CODEC_REG_BASE+(0x0020<<1)) macro