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Searched refs:REG_RVD_43_L (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A DhalPNL.c3480 W2BYTEMSK(REG_RVD_43_L, 0x0C00, 0x1F00); in MHal_PNL_Init_XC_Clk()
3510 W2BYTEMSK(REG_RVD_43_L, 0x0400, 0x1F00); in MHal_PNL_Init_XC_Clk()
3546 …W2BYTEMSK(REG_RVD_43_L, 0x0C00, 0x1F00); //[12:8]reg_ckg_odclk_2p, [11]Select clock source, 1: LP… in MHal_PNL_Init_XC_Clk()
3557 W2BYTEMSK(REG_RVD_43_L, 0x0400, 0x1F00); in MHal_PNL_Init_XC_Clk()
3615 W2BYTEMSK(REG_RVD_43_L, 0x0200, 0x0200); //FIXME:patch for PIP in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h221 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A DhalPNL.c3507 W2BYTEMSK(REG_RVD_43_L, 0x0C00, 0x1F00); in MHal_PNL_Init_XC_Clk()
3537 W2BYTEMSK(REG_RVD_43_L, 0x0400, 0x1F00); in MHal_PNL_Init_XC_Clk()
3573 …W2BYTEMSK(REG_RVD_43_L, 0x0C00, 0x1F00); //[12:8]reg_ckg_odclk_2p, [11]Select clock source, 1: LP… in MHal_PNL_Init_XC_Clk()
3584 W2BYTEMSK(REG_RVD_43_L, 0x0400, 0x1F00); in MHal_PNL_Init_XC_Clk()
3642 W2BYTEMSK(REG_RVD_43_L, 0x0200, 0x0200); //FIXME:patch for PIP in MHal_PNL_Init_XC_Clk()
H A DhalPNL.h221 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A DhalPNL.h219 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A DhalPNL.h212 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) macro
H A DhalPNL.c2746 W2BYTEMSK(REG_RVD_43_L, 0x0400,0x0F00); //for scaler tgen in MHal_PNL_Init_XC_Clk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A DhalPNL.h219 #define REG_RVD_43_L (REG_RVD_BASE + 0x86) macro