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Searched refs:REG_MHL_CBUS_19 (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_mhl.h107 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_mhl.h107 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/
H A DhwregMHL.h130 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/
H A DhwregMHL.h130 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/
H A DhalMHL.c202 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
2633 …W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // … in mhal_mhl_LoadDeviceCapability()
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/
H A DhalMHL.c202 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
2633 …W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // … in mhal_mhl_LoadDeviceCapability()
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
H A DhalMHL.c186 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
3087 …W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // … in mhal_mhl_LoadDeviceCapability()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
H A DhalMHL.c186 …{REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1…
3063 …W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // … in mhal_mhl_LoadDeviceCapability()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/
H A DhwregMHL.h141 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_pm_sleep.h552 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_pm_sleep.h550 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_pm_sleep.h551 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_pm_sleep.h552 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_pm_sleep.h552 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_pm_sleep.h553 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_pm_sleep.h553 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_pm_sleep.h552 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) macro

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