| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/mhl/internal/ |
| H A D | halMHL.c | 3205 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
3220 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3222 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 127 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/mhl/internal/ |
| H A D | halMHL.c | 3202 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
3217 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3219 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 127 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/mhl/internal/ |
| H A D | halMHL.c | 3651 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
3666 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3668 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/mhl/internal/ |
| H A D | halMHL.c | 3651 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
3666 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
3668 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/mhl/internal/ |
| H A D | halMHL.c | 4096 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4111 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4113 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/mhl/internal/ |
| H A D | halMHL.c | 4120 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4135 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4137 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/mhl/internal/ |
| H A D | halMHL.c | 4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/mhl/internal/ |
| H A D | halMHL.c | 4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/mhl/internal/ |
| H A D | halMHL.c | 4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/mhl/internal/ |
| H A D | halMHL.c | 4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/mhl/internal/ |
| H A D | halMHL.c | 4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE); in mhal_mhl_CheckSRAMReceiveBuffer()
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15)); in mhal_mhl_GetSRAMReceiveData()
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14)); in mhal_mhl_GetSRAMReceiveData()
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| H A D | hwregMHL.h | 132 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_pm_sleep.h | 543 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 541 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_pm_sleep.h | 542 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) macro
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