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Searched refs:REG_HDCP_DUAL_P0_BASE (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h590 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3889 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3890 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3891 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3892 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3893 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3894 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3895 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3896 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3897 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3898 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h572 #define REG_HDCP_DUAL_P0_BASE 0x172200UL macro
575 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE
578 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE
581 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3889 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3890 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3891 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3892 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3893 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3894 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3895 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3896 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3897 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3898 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h574 #define REG_HDCP_DUAL_P0_BASE 0x172200UL macro
577 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE
580 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE
583 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE
H A Dmhal_xc_chip_config.h.0573 #define REG_HDCP_DUAL_P0_BASE 0x172200UL
576 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE
579 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE
582 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3889 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3890 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3891 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3892 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3893 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3894 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3895 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3896 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3897 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3898 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h566 #define REG_HDCP_DUAL_P0_BASE 0x172200UL macro
569 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE
572 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE
575 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3889 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3890 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3891 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3892 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3893 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3894 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3895 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3896 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3897 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3898 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h572 #define REG_HDCP_DUAL_P0_BASE 0x172200UL macro
575 #define REG_HDCP_DUAL_P1_BASE REG_HDCP_DUAL_P0_BASE
578 #define REG_HDCP_DUAL_P2_BASE REG_HDCP_DUAL_P0_BASE
581 #define REG_HDCP_DUAL_P3_BASE REG_HDCP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h550 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h577 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h548 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3888 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3889 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3890 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3891 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3892 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3893 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3894 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3895 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3896 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3897 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h531 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h636 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00)
3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01)
3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02)
3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03)
3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04)
3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05)
3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06)
3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07)
3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08)
3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h624 #define REG_HDCP_DUAL_P0_BASE 0x171200UL macro

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