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Searched refs:REG_FIQ_PENDING_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DhalCHIP.c272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in CHIP_DetectIRQSource()
1340 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_DetectIRQSource()
1428 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in __CHIP_HISR1()
H A DregCHIP.h123 #define REG_FIQ_PENDING_L 0x002c macro
162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DhalCHIP.c272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in CHIP_DetectIRQSource()
1340 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_DetectIRQSource()
1428 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in __CHIP_HISR1()
H A DregCHIP.h123 #define REG_FIQ_PENDING_L 0x002c macro
162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DhalCHIP.c272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in CHIP_DetectIRQSource()
1327 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_DetectIRQSource()
1415 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in __CHIP_HISR1()
H A DregCHIP.h123 #define REG_FIQ_PENDING_L 0x002c macro
162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DhalCHIP.c272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in CHIP_DetectIRQSource()
1340 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_DetectIRQSource()
1428 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in __CHIP_HISR1()
H A DregCHIP.h123 #define REG_FIQ_PENDING_L 0x002c macro
162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DhalCHIP.c272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in CHIP_DetectIRQSource()
1340 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_DetectIRQSource()
1428 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in __CHIP_HISR1()
H A DregCHIP.h123 #define REG_FIQ_PENDING_L 0x002c macro
162 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
168 #define REG_FIQ_PENDING_L 0x002c macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
167 #define REG_FIQ_PENDING_L 0x002c macro
H A DhalCHIP.c269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
167 #define REG_FIQ_PENDING_L 0x002c macro
H A DhalCHIP.c269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
167 #define REG_FIQ_PENDING_L 0x002c macro
H A DhalCHIP.c269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
168 #define REG_FIQ_PENDING_L 0x002c macro
H A DhalCHIP.c269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DregCHIP.h142 #define REG_FIQ_PENDING_L 0x002c macro
167 #define REG_FIQ_PENDING_L 0x002c macro
H A DhalCHIP.c269 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DregCHIP.h130 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DregCHIP.h130 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DregCHIP.h130 #define REG_FIQ_PENDING_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c247 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L); in _CHIP_LISR1()

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