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Searched refs:REG_FIQ_CLEAR_L (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/mxlib/hal/M7621/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
164 #define REG_FIQ_CLEAR_L 0x002c macro
/utopia/UTPA2-700.0.x/mxlib/hal/maxim/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
163 #define REG_FIQ_CLEAR_L 0x002c macro
H A DhalCHIP.c526 IRQ_REG(REG_FIQ_CLEAR_L) = (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/manhattan/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
163 #define REG_FIQ_CLEAR_L 0x002c macro
H A DhalCHIP.c526 IRQ_REG(REG_FIQ_CLEAR_L) = (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/marcus/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
163 #define REG_FIQ_CLEAR_L 0x002c macro
H A DhalCHIP.c526 IRQ_REG(REG_FIQ_CLEAR_L) = (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/M7821/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
164 #define REG_FIQ_CLEAR_L 0x002c macro
H A DhalCHIP.c526 IRQ_REG(REG_FIQ_CLEAR_L) = (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/maserati/
H A DregCHIP.h138 #define REG_FIQ_CLEAR_L 0x002c macro
163 #define REG_FIQ_CLEAR_L 0x002c macro
H A DhalCHIP.c526 IRQ_REG(REG_FIQ_CLEAR_L) = (0x1 << (u8VectorIndex-E_FIQL_START) ); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/curry/
H A DregCHIP.h119 #define REG_FIQ_CLEAR_L 0x002c macro
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1750 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/k7u/
H A DregCHIP.h119 #define REG_FIQ_CLEAR_L 0x002c macro
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1763 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/k6lite/
H A DregCHIP.h119 #define REG_FIQ_CLEAR_L 0x002c macro
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1763 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/k6/
H A DregCHIP.h119 #define REG_FIQ_CLEAR_L 0x002c macro
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1763 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/kano/
H A DregCHIP.h119 #define REG_FIQ_CLEAR_L 0x002c macro
152 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
1763 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()
/utopia/UTPA2-700.0.x/mxlib/hal/mustang/
H A DregCHIP.h125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/messi/
H A DregCHIP.h125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
/utopia/UTPA2-700.0.x/mxlib/hal/mainz/
H A DregCHIP.h125 #define REG_FIQ_CLEAR_L (REG_INT_BASE_ADDR + 0x000c) macro
H A DhalCHIP.c508 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START)); in CHIP_DisableIRQ()

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