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Searched refs:REG_DVI_RSV_DUAL_P0_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h589 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3824 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3826 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3827 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3828 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3829 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3830 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3831 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3832 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h571 #define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL macro
574 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE
577 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE
580 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h549 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3824 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3826 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3827 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3828 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3829 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3830 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3831 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3832 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h573 #define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL macro
576 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE
579 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE
582 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE
H A Dmhal_xc_chip_config.h.0572 #define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL
575 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE
578 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE
581 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h576 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3824 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3826 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3827 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3828 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3829 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3830 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3831 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3832 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h565 #define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL macro
568 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE
571 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE
574 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3823 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3824 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3825 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3826 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3827 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3828 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3829 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3830 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3831 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3832 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h571 #define REG_DVI_RSV_DUAL_P0_BASE 0x172100UL macro
574 #define REG_DVI_RSV_DUAL_P1_BASE REG_DVI_RSV_DUAL_P0_BASE
577 #define REG_DVI_RSV_DUAL_P2_BASE REG_DVI_RSV_DUAL_P0_BASE
580 #define REG_DVI_RSV_DUAL_P3_BASE REG_DVI_RSV_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h547 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3822 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3823 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3824 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3825 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3826 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3827 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3828 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3829 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3830 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3831 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h530 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h623 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h635 #define REG_DVI_RSV_DUAL_P0_BASE 0x171100UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
[all …]

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