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Searched refs:REG_CKG_OSDC (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h619 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h619 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h914 #define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h920 #define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h913 #define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h907 #define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB ) macro
H A Dmhal_xc_chip_config.h.0906 #define REG_CKG_OSDC (REG_CHIPTOP_BASE + 0xAB )
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h786 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h893 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h854 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h905 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h840 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h910 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h897 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c5800 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
5808 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
5809 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
5813 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
5814 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
5942 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c6443 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
6451 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6452 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6456 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6457 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6585 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c6523 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
6531 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6532 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6536 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6537 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6665 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c6970 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
6978 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6979 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6983 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6984 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7112 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c6990 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
6998 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
6999 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7003 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
7004 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7132 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c7268 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
7276 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
7277 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7281 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
7282 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7410 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c7268 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK); in MHAL_SC_set_osdc_clk_mux()
7276 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
7277 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7281 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert in MHAL_SC_enable_osdc()
7282 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7410 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()