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Searched refs:REG_CKG_FMCLK (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c2251 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2252 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2257 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2258 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2263 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c2231 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2232 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2237 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2238 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2243 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c2318 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2319 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2324 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2325 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2330 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c6326 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
6327 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED); in Hal_SC_set_fmclk()
6328 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT); in Hal_SC_set_fmclk()
6332 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c2494 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2495 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2500 MDrv_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
2501 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2506 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7087 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
7088 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED); in Hal_SC_set_fmclk()
7089 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT); in Hal_SC_set_fmclk()
7093 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c3130 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3131 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3136 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3137 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3142 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c3081 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3082 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3087 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3088 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3093 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7617 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
7618 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED); in Hal_SC_set_fmclk()
7619 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT); in Hal_SC_set_fmclk()
7623 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c3132 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3133 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3138 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3139 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3144 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c3085 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3086 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3091 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3092 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3097 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7640 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
7641 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED); in Hal_SC_set_fmclk()
7642 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT); in Hal_SC_set_fmclk()
7646 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h639 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h645 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h645 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h647 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB ) macro
H A Dmhal_xc_chip_config.h.0646 #define REG_CKG_FMCLK (REG_CHIPTOP_BASE + 0xBB )
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h621 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h721 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h681 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h733 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h671 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h738 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h725 #define REG_CKG_FMCLK (REG_CLKGEN0_BASE + 0xBB ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c7049 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
7050 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED); in Hal_SC_set_fmclk()
7051 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT); in Hal_SC_set_fmclk()
7055 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock in Hal_SC_set_fmclk()

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