| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | mhal_xc_chip_config.h | 502 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | mhal_xc_chip_config.h | 502 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | mhal_xc_chip_config.h | 657 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | mhal_xc_chip_config.h | 655 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | mhal_xc_chip_config.h | 668 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | mhal_xc_chip_config.h | 674 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | mhal_xc_chip_config.h | 674 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | mhal_xc_chip_config.h | 676 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p… macro
|
| H A D | mhal_xc_chip_config.h.0 | 675 #define REG_CKG_FICLK2_F2 (REG_CHIPTOP_BASE + 0xA3 ) // scaling line buffer, set to fclk if p…
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | mhal_xc_chip_config.h | 652 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | mhal_xc_chip_config.h | 752 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 712 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/ |
| H A D | mhal_xc_chip_config.h | 764 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | mhal_xc_chip_config.h | 702 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/ |
| H A D | mhal_xc_chip_config.h | 769 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | mhal_xc_chip_config.h | 756 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if … macro
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_sc.c | 3647 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
3649 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/ |
| H A D | mhal_sc.c | 3687 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
3689 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_sc.c | 5070 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
5072 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_sc.c | 5206 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
5208 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 6312 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
6314 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_sc.c | 7035 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
7037 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_sc.c | 7073 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
7075 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_sc.c | 7603 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
7605 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|
| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_sc.c | 7626 … MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED); in Hal_SC_set_ficlk2()
7628 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK); in Hal_SC_set_ficlk2()
|