Searched refs:REG_CKG0_ODCLK_SOURCE (Results 1 – 4 of 4) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/include/ |
| H A D | regHDMITx.h | 153 #define REG_CKG0_ODCLK_SOURCE 0x4AU macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/include/ |
| H A D | regHDMITx.h | 153 #define REG_CKG0_ODCLK_SOURCE 0x4AU macro
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/ |
| H A D | halHDMITx.c | 943 …MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x0010, 0x0010); //ODCLK source fr… in MHal_HDMITx_InitSeq()
2144 … MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0001);//Repetition times in MHal_HDMITx_SetVideoOutputMode()
2151 … MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0000);//Repetition times in MHal_HDMITx_SetVideoOutputMode()
|
| /utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/ |
| H A D | halHDMITx.c | 998 …MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x0010, 0x0010); //ODCLK source fr… in MHal_HDMITx_InitSeq()
2259 … MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0001);//Repetition times in MHal_HDMITx_SetVideoOutputMode()
2266 … MHal_HDMITx_Mask_Write(CLKGEN0_REG_BASE, REG_CKG0_ODCLK_SOURCE, 0x000F, 0x0000);//Repetition times in MHal_HDMITx_SetVideoOutputMode()
|