Home
last modified time | relevance | path

Searched refs:REG_ADC_CLKGEN0_20_L (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_adc_atop.h377 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c128 { DRV_ADC_REG(REG_ADC_CLKGEN0_20_L), 0x10, 0x00, 0x10/*All*/, },
H A Dhwreg_adc_atop.h628 #define REG_ADC_CLKGEN0_20_L (REG_CLKGEN0_BASE + 0x40) macro