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Searched refs:REG_ADC_ATOP_39_H (Results 1 – 25 of 31) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1695 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1704 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1695 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1704 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1695 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1704 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1646 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1655 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1711 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1720 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1711 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1720 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1711 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1720 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1760 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1769 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1711 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1720 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1711 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1720 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c42 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*All*/, },
1760 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x00/*SW_UG*/,
1769 { DRV_ADC_REG(REG_ADC_ATOP_39_H), 0x20, 0x00, 0x20/*SW_UG*/,
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_atop.h220 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) macro

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