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Searched refs:REG_ADC_ATOP_02_L (Results 1 – 25 of 41) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_mux.c264 W2BYTEMSK(REG_ADC_ATOP_02_L, PortId , BITMASK(3:0) ); in Hal_SC_mux_set_adc_y_mux()
270 W2BYTEMSK(REG_ADC_ATOP_02_L, (PortId<<4), BITMASK(7:4) ); // ADC_VD_CMUX_MASK in Hal_SC_mux_set_adc_c_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_mux.c264 W2BYTEMSK(REG_ADC_ATOP_02_L, PortId , BITMASK(3:0) ); in Hal_SC_mux_set_adc_y_mux()
270 W2BYTEMSK(REG_ADC_ATOP_02_L, (PortId<<4), BITMASK(7:4) ); // ADC_VD_CMUX_MASK in Hal_SC_mux_set_adc_c_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_mux.c264 W2BYTEMSK(REG_ADC_ATOP_02_L, PortId , BITMASK(3:0) ); in Hal_SC_mux_set_adc_y_mux()
270 W2BYTEMSK(REG_ADC_ATOP_02_L, (PortId<<4), BITMASK(7:4) ); // ADC_VD_CMUX_MASK in Hal_SC_mux_set_adc_c_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_mux.c264 W2BYTEMSK(REG_ADC_ATOP_02_L, PortId , BITMASK(3:0) ); in Hal_SC_mux_set_adc_y_mux()
270 W2BYTEMSK(REG_ADC_ATOP_02_L, (PortId<<4), BITMASK(7:4) ); // ADC_VD_CMUX_MASK in Hal_SC_mux_set_adc_c_mux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_adctbl.c235 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
259 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dmhal_adctbl.c235 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
259 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dmhal_adctbl.c235 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
259 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_adctbl.c235 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
259 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_adctbl.c260 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0x0F, 0x01, 0x00/*RGB0_Sync*/,
288 { DRV_ADC_REG(REG_ADC_ATOP_02_L), 0xF0, 0x01, 0x00/*RGB0_Sync*/,
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_adc_atop.h109 #define REG_ADC_ATOP_02_L (REG_ADC_ATOP_BASE + 0x04) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_adc.c923 W2BYTEMSK(REG_ADC_ATOP_02_L, 0, BIT(9)); // reg_mux_c_en in _Hal_ADC_SCART_SV_RGB_switch()
931 W2BYTEMSK(REG_ADC_ATOP_02_L, BIT(9), BIT(9)); // reg_mux_c_en in _Hal_ADC_SCART_SV_RGB_switch()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_adc.c923 W2BYTEMSK(REG_ADC_ATOP_02_L, 0, BIT(9)); // reg_mux_c_en in _Hal_ADC_SCART_SV_RGB_switch()
931 W2BYTEMSK(REG_ADC_ATOP_02_L, BIT(9), BIT(9)); // reg_mux_c_en in _Hal_ADC_SCART_SV_RGB_switch()

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