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Searched refs:OTV0_REG_CTRL_BASE (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/otv/
H A DregOTV.h154 #define OTV0_REG_CTRL_BASE OTV_BANK0_REG_CTRL_BASE macro
159 #define OTV0_PIDFLT_BASE (OTV0_REG_CTRL_BASE+0x2C)
164 #define OTV0_EVENT_MASK_BASE (OTV0_REG_CTRL_BASE+0xC0)
H A DhalOTV.c172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/otv/
H A DregOTV.h154 #define OTV0_REG_CTRL_BASE OTV_BANK0_REG_CTRL_BASE macro
159 #define OTV0_PIDFLT_BASE (OTV0_REG_CTRL_BASE+0x2C)
164 #define OTV0_EVENT_MASK_BASE (OTV0_REG_CTRL_BASE+0xC0)
H A DhalOTV.c172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/otv/
H A DregOTV.h154 #define OTV0_REG_CTRL_BASE OTV_BANK0_REG_CTRL_BASE macro
159 #define OTV0_PIDFLT_BASE (OTV0_REG_CTRL_BASE+0x2C)
164 #define OTV0_EVENT_MASK_BASE (OTV0_REG_CTRL_BASE+0xC0)
H A DhalOTV.c172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/otv/
H A DregOTV.h154 #define OTV0_REG_CTRL_BASE OTV_BANK0_REG_CTRL_BASE macro
159 #define OTV0_PIDFLT_BASE (OTV0_REG_CTRL_BASE+0x2C)
164 #define OTV0_EVENT_MASK_BASE (OTV0_REG_CTRL_BASE+0xC0)
H A DhalOTV.c172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()