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Searched refs:MIU_REG_BASE (Results 1 – 25 of 64) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/miu/hal/curry/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
127 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
128 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
129 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
131 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
132 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
133 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
135 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
136 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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/utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
127 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
128 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
129 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
131 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
132 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
133 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
135 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
136 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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/utopia/UTPA2-700.0.x/modules/miu/hal/maldives/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200) macro
127 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
128 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
129 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
130 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
131 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
132 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
133 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
135 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
136 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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H A DhalMIU.c989 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1113 MS_U32 u32Reg = (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1277 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_MaskReq()
1302 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_UnMaskReq()
1326 u32Reg = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1548 return (HAL_MIU_ReadByte(MIU_REG_BASE+0x04) & REG_MIU_I64_MODE) ? (64) : (128); in HAL_MIU_IsI64Mode()
1576 u32RegAddr += (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
1605 u32Reg += (u8MiuDev == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_SetHPriorityMask()
/utopia/UTPA2-700.0.x/modules/miu/hal/macan/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
132 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
133 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
134 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
135 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
136 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
137 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
138 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
140 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
141 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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H A DhalMIU.c1014 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1206 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1381 u32Reg += MIU_REG_BASE; in HAL_MIU_MaskReq()
1423 u32Reg += MIU_REG_BASE; in HAL_MIU_UnMaskReq()
1465 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1479 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1493 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1507 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1521 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1752 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
132 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
133 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
134 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
135 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
136 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
137 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
138 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
140 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
141 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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H A DhalMIU.c1124 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1342 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1517 u32Reg += MIU_REG_BASE; in HAL_MIU_MaskReq()
1559 u32Reg += MIU_REG_BASE; in HAL_MIU_UnMaskReq()
1601 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1615 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1629 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1643 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1657 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1888 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
135 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
136 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
137 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
138 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
139 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
140 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
141 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
143 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
144 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
135 #define DDR_FREQ_SET_0 (MIU_REG_BASE+0x20) // 0x1220
136 #define DDR_FREQ_SET_1 (MIU_REG_BASE+0x21) //0x1221
137 #define DDR_FREQ_DIV_1 (MIU_REG_BASE+0x25) //0x1225
138 #define DDR_FREQ_INPUT_DIV_2 (MIU_REG_BASE+0x26) //0x1226
139 #define DDR_FREQ_LOOP_DIV_2 (MIU_REG_BASE+0x27) //0x1227
140 #define DDR_CLK_SELECT (MIU_REG_BASE+0x3e) //0x123E
141 #define DDR_FREQ_STATUS (MIU_REG_BASE+0x3f) //0x123F
143 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
144 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k6lite/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
126 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
127 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
128 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
129 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
130 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
131 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
133 #define MIU_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x46 + 0x20*G…
134 #define MIU_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x48 + 0x20*G…
137 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k6/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
126 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
127 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
128 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
129 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
130 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
131 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
133 #define MIU_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x46 + 0x20*G…
134 #define MIU_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x48 + 0x20*G…
137 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k7u/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
126 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
127 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
128 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
129 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
130 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
131 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
133 #define MIU_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x46 + 0x20*G…
134 #define MIU_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU_REG_BASE + 0x48 + 0x20*G…
137 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
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/utopia/UTPA2-700.0.x/modules/miu/hal/messi/miu/
H A DregMIU.h92 #define MIU_REG_BASE (0x1200UL) macro
116 #define MIU_RQ0L_MASK (MIU_REG_BASE + 0x46)
117 #define MIU_RQ0H_MASK (MIU_REG_BASE + 0x47)
118 #define MIU_RQ1L_MASK (MIU_REG_BASE + 0x66)
119 #define MIU_RQ1H_MASK (MIU_REG_BASE + 0x67)
120 #define MIU_RQ2L_MASK (MIU_REG_BASE + 0x86)
121 #define MIU_RQ2H_MASK (MIU_REG_BASE + 0x87)
126 #define MIU_PROTECT_EN (MIU_REG_BASE + 0xD2)
127 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE + 0xD3)
137 #define MIU_PROTECT0_ID0 (MIU_REG_BASE + 0x2E)
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H A DhalMIU.c1099 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1291 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1506 u32Reg += MIU_REG_BASE; in HAL_MIU_MaskReq()
1579 u32Reg += MIU_REG_BASE; in HAL_MIU_UnMaskReq()
1622 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1636 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1650 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1664 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1678 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1909 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/mooney/miu/
H A DregMIU.h92 #define MIU_REG_BASE (0x1200UL) macro
116 #define MIU_RQ0L_MASK (MIU_REG_BASE + 0x46)
117 #define MIU_RQ0H_MASK (MIU_REG_BASE + 0x47)
118 #define MIU_RQ1L_MASK (MIU_REG_BASE + 0x66)
119 #define MIU_RQ1H_MASK (MIU_REG_BASE + 0x67)
120 #define MIU_RQ2L_MASK (MIU_REG_BASE + 0x86)
121 #define MIU_RQ2H_MASK (MIU_REG_BASE + 0x87)
126 #define MIU_PROTECT_EN (MIU_REG_BASE + 0xD2)
127 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE + 0xD3)
137 #define MIU_PROTECT0_ID0 (MIU_REG_BASE + 0x2E)
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H A DhalMIU.c1058 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1250 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1465 u32Reg += MIU_REG_BASE; in HAL_MIU_MaskReq()
1538 u32Reg += MIU_REG_BASE; in HAL_MIU_UnMaskReq()
1581 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1595 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1609 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1623 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1637 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1868 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/mainz/miu/
H A DregMIU.h92 #define MIU_REG_BASE (0x1200UL) macro
116 #define MIU_RQ0L_MASK (MIU_REG_BASE + 0x46)
117 #define MIU_RQ0H_MASK (MIU_REG_BASE + 0x47)
118 #define MIU_RQ1L_MASK (MIU_REG_BASE + 0x66)
119 #define MIU_RQ1H_MASK (MIU_REG_BASE + 0x67)
120 #define MIU_RQ2L_MASK (MIU_REG_BASE + 0x86)
121 #define MIU_RQ2H_MASK (MIU_REG_BASE + 0x87)
126 #define MIU_PROTECT_EN (MIU_REG_BASE + 0xD2)
127 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE + 0xD3)
137 #define MIU_PROTECT0_ID0 (MIU_REG_BASE + 0x2E)
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H A DhalMIU.c1099 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1291 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1506 u32Reg += MIU_REG_BASE; in HAL_MIU_MaskReq()
1579 u32Reg += MIU_REG_BASE; in HAL_MIU_UnMaskReq()
1622 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1636 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1650 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1664 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1678 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1909 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
[all …]
/utopia/UTPA2-700.0.x/modules/miu/hal/mustang/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200) macro
125 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
126 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
127 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
128 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
129 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
130 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
134 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
135 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3)
144 #define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2E)
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H A DhalMIU.c1073 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1245 u32Reg = MIU_REG_BASE; in HAL_MIU_ProtectEx()
1369 MS_U32 u32Reg = (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1525 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_MaskReq()
1550 u32Reg += (u8Miu == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_UnMaskReq()
1574 u32Reg = MIU_REG_BASE + REG_MIU_SELX(MIU_GET_CLIENT_GROUP(sVal)); in HAL_MIU_SelMIU()
1796 return (HAL_MIU_ReadByte(MIU_REG_BASE+0x04) & REG_MIU_I64_MODE) ? (64) : (128); in HAL_MIU_IsI64Mode()
1824 u32RegAddr += (u8MiuDev) ? MIU1_REG_BASE : MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
1853 u32Reg += (u8MiuDev == 0) ? MIU_REG_BASE : MIU1_REG_BASE; in HAL_MIU_SetHPriorityMask()
/utopia/UTPA2-700.0.x/modules/miu/hal/M7621/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
127 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
128 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
129 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
130 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
131 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
132 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
138 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
139 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3)
149 #define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2E)
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H A DhalMIU.c1038 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1186 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1363 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : MIU1_REG_BASE); in HAL_MIU_MaskReq()
1415 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : MIU1_REG_BASE); in HAL_MIU_UnMaskReq()
1487 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(u32IdGroup); in HAL_MIU_SelMIU()
1732 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
1773 u32Reg += MIU_REG_BASE; in HAL_MIU_SetHPriorityMask()
/utopia/UTPA2-700.0.x/modules/miu/hal/maxim/miu/
H A DregMIU.h117 #define MIU_REG_BASE (0x1200UL) macro
127 #define MIU_RQ0L_MASK (MIU_REG_BASE+0x46)
128 #define MIU_RQ0H_MASK (MIU_REG_BASE+0x47)
129 #define MIU_RQ1L_MASK (MIU_REG_BASE+0x66)
130 #define MIU_RQ1H_MASK (MIU_REG_BASE+0x67)
131 #define MIU_RQ2L_MASK (MIU_REG_BASE+0x86)
132 #define MIU_RQ2H_MASK (MIU_REG_BASE+0x87)
138 #define MIU_PROTECT_EN (MIU_REG_BASE+0xD2)
139 #define MIU_PROTECT_DDR_SIZE (MIU_REG_BASE+0xD3)
149 #define MIU_PROTECT0_ID0 (MIU_REG_BASE+0x2E)
[all …]
H A DhalMIU.c1032 u32Reg = MIU_REG_BASE; in HAL_MIU_Protect()
1180 u32Reg = MIU_REG_BASE; in HAL_MIU_GetProtectInfo()
1357 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : MIU1_REG_BASE); in HAL_MIU_MaskReq()
1409 u32RegBase = (u8Miu == E_MIU_0 ? MIU_REG_BASE : MIU1_REG_BASE); in HAL_MIU_UnMaskReq()
1481 u32Reg0 = MIU_REG_BASE + REG_MIU_SELX(u32IdGroup); in HAL_MIU_SelMIU()
1726 u32RegAddr += MIU_REG_BASE; in HAL_MIU_SetGroupPriority()
1767 u32Reg += MIU_REG_BASE; in HAL_MIU_SetHPriorityMask()

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