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Searched refs:MIU1_REG_HVD_BASE2 (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h390 #define MIU1_REG_HVD_BASE2 (0x62200) macro
403 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
404 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h398 #define MIU1_REG_HVD_BASE2 (0x62200) macro
414 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
415 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h406 #define MIU1_REG_HVD_BASE2 (0x62200) macro
422 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
423 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h406 #define MIU1_REG_HVD_BASE2 (0x62200) macro
422 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
423 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h406 #define MIU1_REG_HVD_BASE2 (0x62200) macro
422 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
423 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
439 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
440 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
442 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
443 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
439 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
440 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
442 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
443 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
439 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
440 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h424 #define MIU1_REG_HVD_BASE2 (0x62200) macro
440 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
441 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
442 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
443 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
442 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
443 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h426 #define MIU1_REG_HVD_BASE2 (0x62200) macro
442 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
443 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h538 #define MIU1_REG_HVD_BASE2 (0x62200) macro
551 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
552 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h596 #define MIU1_REG_HVD_BASE2 (0x62200) macro
629 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
630 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h597 #define MIU1_REG_HVD_BASE2 (0x62200) macro
630 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
631 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h613 #define MIU1_REG_HVD_BASE2 (0x62200) macro
633 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
634 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h597 #define MIU1_REG_HVD_BASE2 (0x62200) macro
630 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
631 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h598 #define MIU1_REG_HVD_BASE2 (0x62200) macro
631 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
632 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h596 #define MIU1_REG_HVD_BASE2 (0x62200) macro
629 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
630 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h613 #define MIU1_REG_HVD_BASE2 (0x62200) macro
633 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
634 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h597 #define MIU1_REG_HVD_BASE2 (0x62200) macro
630 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
631 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h642 #define MIU1_REG_HVD_BASE2 (0x62200) macro
673 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
674 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h625 #define MIU1_REG_HVD_BASE2 (0x62200) macro
657 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1))
658 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1))

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