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Searched refs:MIU1_REG_BASE (Results 1 – 25 of 131) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/miu/hal/curry/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
190 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
191 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
192 #define MIU1_PROTECT_SDR_LIKE (MIU1_REG_BASE+0xD3)
193 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
194 #define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46 + 0x20…
195 #define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48 + 0x20…
198 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
199 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
200 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
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/utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
190 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
191 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
192 #define MIU1_PROTECT_SDR_LIKE (MIU1_REG_BASE+0xD3)
193 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
194 #define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46 + 0x20…
195 #define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48 + 0x20…
198 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
199 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
200 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k6lite/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
173 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
174 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
175 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
176 #define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46 + 0x20…
177 #define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48 + 0x20…
180 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
181 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
182 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
183 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k6/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
173 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
174 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
175 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
176 #define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46 + 0x20…
177 #define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48 + 0x20…
180 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
181 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
182 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
183 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
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/utopia/UTPA2-700.0.x/modules/miu/hal/k7u/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
173 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
174 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
175 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
176 #define MIU1_RQX_MASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x46 + 0x20…
177 #define MIU1_RQX_HPMASK(Reg, Group) (Reg = (Group < 4 )? (MIU1_REG_BASE + 0x48 + 0x20…
180 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
181 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
182 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
183 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
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/utopia/UTPA2-700.0.x/modules/miu/hal/macan/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
193 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
194 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
195 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
196 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
197 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
198 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
199 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
200 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
201 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/maldives/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600) macro
186 #define MIU1_RQ1L_MASK (MIU1_REG_BASE+0x66)
187 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
188 #define MIU1_PROTECT_SDR_LIKE (MIU1_REG_BASE+0xD3)
189 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
191 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
192 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
193 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
194 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
195 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
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/utopia/UTPA2-700.0.x/modules/miu/hal/mustang/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600) macro
168 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
169 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
171 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
172 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
173 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
174 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
175 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
176 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
177 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/M7621/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
172 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
173 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
174 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
175 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
176 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
177 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
178 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
179 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
180 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/maxim/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
172 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
173 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
174 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
175 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
176 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
177 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
178 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
179 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
180 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/messi/miu/
H A DregMIU.h93 #define MIU1_REG_BASE (0x0600UL) macro
162 #define MIU1_PROTECT_EN (MIU1_REG_BASE + 0xD2)
163 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE + 0xD3)
164 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE + 0x2E)
165 #define MIU1_BW_REQUEST (MIU1_REG_BASE + 0x1A)
166 #define MIU1_BW_RESULT (MIU1_REG_BASE + 0x1C)
167 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE + 0x20)
168 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE + 0x22)
169 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE + 0x24)
170 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE + 0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/mooney/miu/
H A DregMIU.h93 #define MIU1_REG_BASE (0x0600UL) macro
162 #define MIU1_PROTECT_EN (MIU1_REG_BASE + 0xD2)
163 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE + 0xD3)
164 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE + 0x2E)
165 #define MIU1_BW_REQUEST (MIU1_REG_BASE + 0x1A)
166 #define MIU1_BW_RESULT (MIU1_REG_BASE + 0x1C)
167 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE + 0x20)
168 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE + 0x22)
169 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE + 0x24)
170 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE + 0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/mainz/miu/
H A DregMIU.h93 #define MIU1_REG_BASE (0x0600UL) macro
162 #define MIU1_PROTECT_EN (MIU1_REG_BASE + 0xD2)
163 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE + 0xD3)
164 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE + 0x2E)
165 #define MIU1_BW_REQUEST (MIU1_REG_BASE + 0x1A)
166 #define MIU1_BW_RESULT (MIU1_REG_BASE + 0x1C)
167 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE + 0x20)
168 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE + 0x22)
169 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE + 0x24)
170 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE + 0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
186 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
187 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
188 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
189 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
190 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
191 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
192 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
193 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
194 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
195 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
196 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
197 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
198 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
199 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
200 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
201 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
202 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
203 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h118 #define MIU1_REG_BASE (0x0600UL) macro
195 #define MIU1_PROTECT_EN (MIU1_REG_BASE+0xD2)
196 #define MIU1_PROTECT_DDR_SIZE (MIU1_REG_BASE+0xD3)
197 #define MIU1_PROTECT0_ID0 (MIU1_REG_BASE+0x2E)
198 #define MIU1_BW_REQUEST (MIU1_REG_BASE+0x1A)
199 #define MIU1_BW_RESULT (MIU1_REG_BASE+0x1C)
200 #define MIU1_PROTECT0_ID_ENABLE (MIU1_REG_BASE+0x20)
201 #define MIU1_PROTECT1_ID_ENABLE (MIU1_REG_BASE+0x22)
202 #define MIU1_PROTECT2_ID_ENABLE (MIU1_REG_BASE+0x24)
203 #define MIU1_PROTECT3_ID_ENABLE (MIU1_REG_BASE+0x26)
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/mvd_v3/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
136 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
137 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
138 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
139 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
140 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
141 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
142 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
143 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/mvd_v3/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
140 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
141 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
142 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
143 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
144 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
145 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
146 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
147 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/mvd_v3/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
140 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
141 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
142 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
143 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
144 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
145 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
146 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
147 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/mvd_v3/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
136 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
137 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
138 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
139 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
140 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
141 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
142 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
143 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/mvd_v3/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
140 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
141 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
142 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
143 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
144 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
145 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
146 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
147 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/mvd_ex/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600UL macro
136 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
137 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
138 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
139 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
140 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
141 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
142 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
143 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DregMVD.h115 #define MIU1_REG_BASE 0x0600 macro
137 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
138 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
139 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
140 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
141 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
142 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
143 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
144 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/mvd_ex/
H A DregMVD_EX.h114 #define MIU1_REG_BASE 0x0600 macro
136 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
137 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
138 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
139 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
140 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
141 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
142 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
143 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DregMVD.h115 #define MIU1_REG_BASE 0x0600 macro
137 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2)
138 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1)
139 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2)
140 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1)
141 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2)
142 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1)
143 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2)
144 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1)

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