Home
last modified time | relevance | path

Searched refs:MIU0_REG_SEL3 (Results 1 – 25 of 89) sorted by relevance

1234

/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c209 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
211 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
212 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
1413 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_Sub_CheckMIUSel()
1415 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_Sub_CheckMIUSel()
1419 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_Sub_CheckMIUSel()
1456 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_Sub_CheckMIUSel()
1458 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_Sub_CheckMIUSel()
1462 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_Sub_CheckMIUSel()
H A DhalHVD.c1511 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4)) ) in HAL_HVD_CheckMIUSel()
1513 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) ); in HAL_HVD_CheckMIUSel()
1517 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(4), BIT(4)); in HAL_HVD_CheckMIUSel()
1554 if( !((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) == BIT(5)) ) in HAL_HVD_CheckMIUSel()
1556 …ufAddr , pHVDCtrl_Hal->MemMap.u32MIU1BaseAddr , (MS_U32)(_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(5)) ); in HAL_HVD_CheckMIUSel()
1560 _HVD_WriteWordMask(MIU0_REG_SEL3 , BIT(5), BIT(5)); in HAL_HVD_CheckMIUSel()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DhalVPU_EX.c257 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
258 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
259 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
261 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
262 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
263 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DhalVPU_EX.c262 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
263 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
264 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
266 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
267 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
268 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DhalVPU_EX.c262 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
263 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
264 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
266 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
267 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
268 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DregVPU.h362 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DregVPU.h362 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DregVPU.h362 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DregVPU_EX.h369 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) macro

1234