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Searched refs:MIU0_REG_HVD_BASE2 (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h387 #define MIU0_REG_HVD_BASE2 (0x61500) macro
396 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
397 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h395 #define MIU0_REG_HVD_BASE2 (0x61500) macro
407 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
408 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h403 #define MIU0_REG_HVD_BASE2 (0x61500) macro
415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
416 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h403 #define MIU0_REG_HVD_BASE2 (0x61500) macro
415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
416 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h403 #define MIU0_REG_HVD_BASE2 (0x61500) macro
415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
416 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
433 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
436 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
433 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
436 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
432 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
433 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h421 #define MIU0_REG_HVD_BASE2 (0x61500) macro
433 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
434 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
436 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
436 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h423 #define MIU0_REG_HVD_BASE2 (0x61500) macro
435 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
436 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h535 #define MIU0_REG_HVD_BASE2 (0x61500) macro
544 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
545 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h593 #define MIU0_REG_HVD_BASE2 (0x61500) macro
622 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
623 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h594 #define MIU0_REG_HVD_BASE2 (0x61500) macro
623 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
624 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h610 #define MIU0_REG_HVD_BASE2 (0x61500) macro
626 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
627 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h594 #define MIU0_REG_HVD_BASE2 (0x61500) macro
623 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
624 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h595 #define MIU0_REG_HVD_BASE2 (0x61500) macro
624 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
625 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h593 #define MIU0_REG_HVD_BASE2 (0x61500) macro
622 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
623 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h610 #define MIU0_REG_HVD_BASE2 (0x61500) macro
626 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
627 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h594 #define MIU0_REG_HVD_BASE2 (0x61500) macro
623 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
624 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h639 #define MIU0_REG_HVD_BASE2 (0x61500) macro
666 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
667 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h622 #define MIU0_REG_HVD_BASE2 (0x61500) macro
650 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1))
651 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1))

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