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Searched refs:MIU (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DhalNDSRASP.c838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
[all …]
H A DhalNDSRASP.h131 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DhalNDSRASP.c838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
[all …]
H A DhalNDSRASP.h131 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DhalNDSRASP.c838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
[all …]
H A DhalNDSRASP.h131 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DhalNDSRASP.c838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
[all …]
H A DhalNDSRASP.h131 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DhalNDSRASP.c838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
[all …]
H A DhalNDSRASP.h131 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/miu/drv/miu/
H A DKconfig3 tristate "MIU"
7 Enable compilation option for driver MIU
H A DMakefile26 DRV_NAME = MIU
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h.0130 // MIU Word (Bytes)
131 #define BYTE_PER_WORD (32) // MIU 128: 16Byte/W, MIU 256: 32Byte/W
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/otv/
H A DhalOTV.h134 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/otv/
H A DhalOTV.h134 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/otv/
H A DhalOTV.h134 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/otv/
H A DhalOTV.h134 #define MIU(_addr_) ((_addr_)>>4) macro
/utopia/UTPA2-700.0.x/modules/flash/drv/flash/serial/
H A DRelease Note.txt20 …fter flash read flushing OCP buffer to avoid non-synchronizing with flash data between OCP and MIU.
/utopia/UTPA2-700.0.x/modules/msos/utopia_core/linux/
H A Dutopia.c259 PREFIX(MIU) \ in UtopiaInit()
/utopia/UTPA2-700.0.x/modules/msos/utopia_core/
H A Dutopia_driver_id.h158 PREFIX(MIU) \
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmvideo.c.01408 …ter can support (IPM_W and IPS_R)/(IPM_R and IPS_W)/(OP_R and OPW) use the same MIU request client
1409 //Others, total 6 MIU request client
/utopia/UTPA2-700.0.x/modules/vdec_v3/api/vdec_v3/
H A DapiVDEC_EX.c.0910 struct CMA_Pool_Init_Param cmaInitParam[2]; // support two MIU