1*53ee8cc1Swenshuai.xi //<MStar Software> 2*53ee8cc1Swenshuai.xi //****************************************************************************** 3*53ee8cc1Swenshuai.xi // MStar Software 4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are 6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. 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MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi // file halOTV.h 97*53ee8cc1Swenshuai.xi // @brief OTV HAL 98*53ee8cc1Swenshuai.xi // @author MStar Semiconductor,Inc. 99*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////////////////////////// 100*53ee8cc1Swenshuai.xi #ifndef __HAL_OTV_H__ 101*53ee8cc1Swenshuai.xi #define __HAL_OTV_H__ 102*53ee8cc1Swenshuai.xi 103*53ee8cc1Swenshuai.xi 104*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 105*53ee8cc1Swenshuai.xi // Driver Compiler Option 106*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 107*53ee8cc1Swenshuai.xi 108*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 109*53ee8cc1Swenshuai.xi // OTV Hardware Abstraction Layer 110*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 111*53ee8cc1Swenshuai.xi 112*53ee8cc1Swenshuai.xi // OTV define 113*53ee8cc1Swenshuai.xi 114*53ee8cc1Swenshuai.xi //######################################################################### 115*53ee8cc1Swenshuai.xi //#### Hardware Capability Macro Start 116*53ee8cc1Swenshuai.xi //######################################################################### 117*53ee8cc1Swenshuai.xi 118*53ee8cc1Swenshuai.xi #define OTV_ENG_NUM 4 119*53ee8cc1Swenshuai.xi #define OTV_PIDFLT_START_NUM 0 120*53ee8cc1Swenshuai.xi #define OTV_PIDFLT_END_NUM 4 121*53ee8cc1Swenshuai.xi #define OTV_PIDFLT_NUM_ALL 4 122*53ee8cc1Swenshuai.xi #define OTV_EVENT_FIFO_DEPTH 32 123*53ee8cc1Swenshuai.xi 124*53ee8cc1Swenshuai.xi 125*53ee8cc1Swenshuai.xi //######################################################################### 126*53ee8cc1Swenshuai.xi //#### Hardware Capability Macro End 127*53ee8cc1Swenshuai.xi //######################################################################### 128*53ee8cc1Swenshuai.xi 129*53ee8cc1Swenshuai.xi 130*53ee8cc1Swenshuai.xi #define OTV_PID_NULL 0x1FFF 131*53ee8cc1Swenshuai.xi 132*53ee8cc1Swenshuai.xi 133*53ee8cc1Swenshuai.xi // HW characteristic 134*53ee8cc1Swenshuai.xi #define MIU(_addr_) ((_addr_)>>4) 135*53ee8cc1Swenshuai.xi 136*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 137*53ee8cc1Swenshuai.xi // Macro of bit operations 138*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 139*53ee8cc1Swenshuai.xi 140*53ee8cc1Swenshuai.xi #if 0 141*53ee8cc1Swenshuai.xi #define HAS_FLAG(flag, bit) ((flag) & (bit)) 142*53ee8cc1Swenshuai.xi #define SET_FLAG(flag, bit) ((flag)|= (bit)) 143*53ee8cc1Swenshuai.xi #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 144*53ee8cc1Swenshuai.xi #define SET_FLAG1(flag, bit) ((flag)| (bit)) 145*53ee8cc1Swenshuai.xi #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 146*53ee8cc1Swenshuai.xi #endif 147*53ee8cc1Swenshuai.xi 148*53ee8cc1Swenshuai.xi #define _SET_(flag, bit) ((flag) | (bit) ) 149*53ee8cc1Swenshuai.xi #define _CLR_(flag, bit) ((flag) & (~(bit))) 150*53ee8cc1Swenshuai.xi 151*53ee8cc1Swenshuai.xi 152*53ee8cc1Swenshuai.xi //////////////////////////////////////////////// 153*53ee8cc1Swenshuai.xi // HAL API 154*53ee8cc1Swenshuai.xi //////////////////////////////////////////////// 155*53ee8cc1Swenshuai.xi 156*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 157*53ee8cc1Swenshuai.xi // For MISC part 158*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 159*53ee8cc1Swenshuai.xi void HAL_OTV_SetBank(MS_VIRT u32BankAddr); 160*53ee8cc1Swenshuai.xi 161*53ee8cc1Swenshuai.xi // OTV Init 162*53ee8cc1Swenshuai.xi void HAL_OTV_Init(MS_U32 u32OTVEng); 163*53ee8cc1Swenshuai.xi 164*53ee8cc1Swenshuai.xi // OTV Config Setting 165*53ee8cc1Swenshuai.xi void HAL_OTV_PktTimerSrcFromPVR_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 166*53ee8cc1Swenshuai.xi void HAL_OTV_PktNumSrcFromPktDemux_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 167*53ee8cc1Swenshuai.xi //void HAL_OTV_FirstPktTimerBase_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 168*53ee8cc1Swenshuai.xi 169*53ee8cc1Swenshuai.xi 170*53ee8cc1Swenshuai.xi // OTV Interrupt 171*53ee8cc1Swenshuai.xi void HAL_OTV_INT_Timer_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 172*53ee8cc1Swenshuai.xi void HAL_OTV_INT_Event_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 173*53ee8cc1Swenshuai.xi void HAL_OTV_INT_SetEventWaterLevel(MS_U32 u32OTVEng, MS_U32 u32EventWaterLevel); 174*53ee8cc1Swenshuai.xi void HAL_OTV_INT_SetTimerWaterLevel(MS_U32 u32OTVEng, MS_U32 u32TimerWaterLevel); 175*53ee8cc1Swenshuai.xi MS_BOOL HAL_OTV_INT_GetEventHW(MS_U32 u32OTVEng); 176*53ee8cc1Swenshuai.xi MS_BOOL HAL_OTV_INT_GetTimerHW(MS_U32 u32OTVEng); 177*53ee8cc1Swenshuai.xi void HAL_OTV_INT_ClrEventHW(MS_U32 u32OTVEng); 178*53ee8cc1Swenshuai.xi void HAL_OTV_INT_ClrTimerHW(MS_U32 u32OTVEng); 179*53ee8cc1Swenshuai.xi 180*53ee8cc1Swenshuai.xi // OTV Event Queue 181*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable); 182*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventNum(MS_U32 u32OTVEng, MS_U32 *pu32EventNum); 183*53ee8cc1Swenshuai.xi MS_BOOL HAL_OTV_EventQ_PopEvent(MS_U32 u32OTVEng); 184*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventDesciptor(MS_U32 u32OTVEng, MS_U32 *pu32EventDesciptor); 185*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventPktNum(MS_U32 u32OTVEng, MS_U32 *pu32EventPktNum); 186*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32EventPktTimer); 187*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventPktPCR(MS_U32 u32OTVEng, MS_U32 *pu32EventPktPCR); 188*53ee8cc1Swenshuai.xi void HAL_OTV_EventQ_GetEventPktPID(MS_U32 u32OTVEng, MS_U16 *pu16EventPktPID); 189*53ee8cc1Swenshuai.xi 190*53ee8cc1Swenshuai.xi 191*53ee8cc1Swenshuai.xi // Get OTV Current Packet Number/TimeStamp 192*53ee8cc1Swenshuai.xi void HAL_OTV_GetCurPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32PktTimer); 193*53ee8cc1Swenshuai.xi void HAL_OTV_GetCurPktNum(MS_U32 u32OTVEng, MS_U32 *pu32PktNum); 194*53ee8cc1Swenshuai.xi 195*53ee8cc1Swenshuai.xi // OTV Pid Filter 196*53ee8cc1Swenshuai.xi void HAL_OTV_SetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 u16Pid); 197*53ee8cc1Swenshuai.xi void HAL_OTV_GetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 *pu16Pid); 198*53ee8cc1Swenshuai.xi void HAL_OTV_SetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 u32FltEvent); 199*53ee8cc1Swenshuai.xi void HAL_OTV_GetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 *pu32FltEvent); 200*53ee8cc1Swenshuai.xi void HAL_OTV_RstFltEvent(MS_U32 u32OTVEng); 201*53ee8cc1Swenshuai.xi 202*53ee8cc1Swenshuai.xi 203*53ee8cc1Swenshuai.xi 204*53ee8cc1Swenshuai.xi 205*53ee8cc1Swenshuai.xi #endif // #ifndef __HAL_OTV_H__ 206