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Searched refs:FIQ_CFG16_INT_ENABLE_MASK (Results 1 – 20 of 20) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/macan/fq/
H A DhalFQ.c259 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
264 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h172 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/manhattan/fq/
H A DhalFQ.c263 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
268 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h172 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/fq/
H A DhalFQ.c252 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
257 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h181 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/fq/
H A DhalFQ.c251 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
256 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h191 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/fq/
H A DhalFQ.c251 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
256 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h189 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/fq/
H A DhalFQ.c274 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Enable()
279 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK)); in HAL_FQ_INT_Disable()
H A DregFQ.h181 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7621/fq/
H A DhalFQ.c317 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
322 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
H A DregFQ.h184 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maxim/fq/
H A DhalFQ.c317 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
322 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
H A DregFQ.h184 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/M7821/fq/
H A DhalFQ.c317 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
322 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
H A DregFQ.h184 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/maserati/fq/
H A DhalFQ.c317 … _SET_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
322 …, _CLR_(_HAL_REG16_R(&(_REGFIQ[u32FQEng].Reg_fiq_config16)), u16Mask & FIQ_CFG16_INT_ENABLE_MASK));
H A DregFQ.h184 #define FIQ_CFG16_INT_ENABLE_MASK 0x00FF macro