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Searched refs:E_INT_FIQ_0x30_START (Results 1 – 3 of 3) sorted by relevance

/utopia/UTPA2-700.0.x/projects/tmplib/include/
H A DMsIRQ.h183 E_INT_FIQ_0x30_START = 0x30, enumerator
184 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0,
185 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1,
186 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2,
187 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3,
188 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4,
189 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5,
190 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6,
191 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7,
192 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8,
[all …]
/utopia/UTPA2-700.0.x/mxlib/include/
H A DMsIRQ.h183 E_INT_FIQ_0x30_START = 0x30, enumerator
184 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0,
185 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1,
186 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2,
187 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3,
188 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4,
189 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5,
190 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6,
191 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7,
192 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8,
[all …]
/utopia/UTPA2-700.0.x/projects/build/
H A Dpreprocess.txt31326 E_INT_FIQ_0x30_START = 0x30,
31327 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0,
31328 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1,
31329 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2,
31330 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3,
31331 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4,
31332 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5,
31333 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6,
31334 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7,
31335 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8,
[all …]