Lines Matching refs:E_INT_FIQ_0x30_START
183 E_INT_FIQ_0x30_START = 0x30, enumerator
184 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0,
185 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1,
186 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2,
187 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3,
188 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4,
189 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5,
190 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6,
191 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7,
192 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8,
193 E_INT_FIQ_INT_CCFL = E_INT_FIQ_0x30_START+9,
194 E_INT_FIQ_INT = E_INT_FIQ_0x30_START+10,
195 E_INT_FIQ_IR = E_INT_FIQ_0x30_START+11,
196 E_INT_FIQ_AFEC_VSYNC = E_INT_FIQ_0x30_START+12,
197 E_INT_FIQ_DEC_DSP2UP = E_INT_FIQ_0x30_START+13,
198 E_INT_FIQ_MIPS_WDT = E_INT_FIQ_0x30_START+14, //U3
199 E_INT_FIQ_DEC_DSP2MIPS = E_INT_FIQ_0x30_START+15,