1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 92 // rights to any and all damages, losses, costs and expenses resulting therefrom. 93 // 94 //////////////////////////////////////////////////////////////////////////////// 95 96 /////////////////////////////////////////////////////////////////////////////////////////////////// 97 /// 98 /// file MsIRQ.h 99 /// @brief MStar IRQ 100 /// @author MStar Semiconductor Inc. 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 104 #ifndef _MS_IRQ_H_ 105 #define _MS_IRQ_H_ 106 107 108 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 //------------------------------------------------------------------------------------------------- 115 // Type and Structure Declaration 116 //------------------------------------------------------------------------------------------------- 117 #define MS_IRQ_MAX (256) //64 IRQs + 64 FIQs 118 #define ENABLE_USB_PORT0 119 #define E_IRQ_FIQ_INVALID 0xFFFF 120 121 // Interrupt related 122 typedef enum 123 { 124 // IRQ 125 E_INT_IRQ_0x00_START = 0x00, 126 E_INT_IRQ_UART0 = E_INT_IRQ_0x00_START+0, 127 E_INT_IRQ_BDMA_CH0 = E_INT_IRQ_0x00_START+1, 128 E_INT_IRQ_BDMA_CH1 = E_INT_IRQ_0x00_START+2, 129 E_INT_IRQ_MVD = E_INT_IRQ_0x00_START+3, 130 E_INT_IRQ_PS = E_INT_IRQ_0x00_START+4, 131 E_INT_IRQ_NFIE = E_INT_IRQ_0x00_START+5, 132 E_INT_IRQ_USB = E_INT_IRQ_0x00_START+6, 133 E_INT_IRQ_UHC = E_INT_IRQ_0x00_START+7, 134 E_INT_IRQ_EC_BRIDGE = E_INT_IRQ_0x00_START+8, 135 E_INT_IRQ_EMAC = E_INT_IRQ_0x00_START+9, 136 E_INT_IRQ_DISP = E_INT_IRQ_0x00_START+10, 137 E_INT_IRQ_DHC = E_INT_IRQ_0x00_START+11, 138 E_INT_IRQ_PMSLEEP = E_INT_IRQ_0x00_START+12, 139 E_INT_IRQ_SBM = E_INT_IRQ_0x00_START+13, 140 E_INT_IRQ_COMB = E_INT_IRQ_0x00_START+14, 141 E_INT_IRQ_ECC_DERR = E_INT_IRQ_0x00_START+15, 142 E_INT_IRQ_0x00_END = 0x0F, 143 144 E_INT_IRQ_0x10_START = 0x10, 145 E_INT_IRQ_TSP2HK = E_INT_IRQ_0x10_START+0, 146 E_INT_IRQ_VE = E_INT_IRQ_0x10_START+1, 147 E_INT_IRQ_CIMAX2MCU = E_INT_IRQ_0x10_START+2, 148 E_INT_IRQ_DC = E_INT_IRQ_0x10_START+3, 149 E_INT_IRQ_GOP = E_INT_IRQ_0x10_START+4, 150 E_INT_IRQ_PCM = E_INT_IRQ_0x10_START+5, 151 E_INT_IRQ_IIC0 = E_INT_IRQ_0x10_START+6, 152 E_INT_IRQ_RTC = E_INT_IRQ_0x10_START+7, 153 E_INT_IRQ_KEYPAD = E_INT_IRQ_0x10_START+8, 154 E_INT_IRQ_PM = E_INT_IRQ_0x10_START+9, 155 E_INT_IRQ_DDC2BI = E_INT_IRQ_0x10_START+10, 156 E_INT_IRQ_SCM = E_INT_IRQ_0x10_START+11, 157 E_INT_IRQ_VBI = E_INT_IRQ_0x10_START+12, 158 E_INT_IRQ_M4VD = E_INT_IRQ_0x10_START+13, 159 E_INT_IRQ_FCIE2RIU = E_INT_IRQ_0x10_START+14, 160 E_INT_IRQ_ADCDVI2RIU = E_INT_IRQ_0x10_START+15, 161 E_INT_IRQ_0x10_END = 0x1F, 162 163 // FIQ 164 E_INT_FIQ_0x20_START = 0x20, 165 E_INT_FIQ_EXTIMER0 = E_INT_FIQ_0x20_START+0, 166 E_INT_FIQ_EXTIMER1 = E_INT_FIQ_0x20_START+1, 167 E_INT_FIQ_WDT = E_INT_FIQ_0x20_START+2, 168 E_INT_FIQ_AEON_TO_8051 = E_INT_FIQ_0x20_START+3, 169 E_INT_FIQ_8051_TO_AEON = E_INT_FIQ_0x20_START+4, 170 E_INT_FIQ_8051_TO_BEON = E_INT_FIQ_0x20_START+5, 171 E_INT_FIQ_BEON_TO_8051 = E_INT_FIQ_0x20_START+6, 172 E_INT_FIQ_BEON_TO_AEON = E_INT_FIQ_0x20_START+7, 173 E_INT_FIQ_AEON_TO_BEON = E_INT_FIQ_0x20_START+8, 174 E_INT_FIQ_JPD = E_INT_FIQ_0x20_START+9, 175 E_INT_FIQ_MENULOAD = E_INT_FIQ_0x20_START+10, 176 E_INT_FIQ_HDMI_NON_PCM = E_INT_FIQ_0x20_START+11, 177 E_INT_FIQ_SPDIF_IN_NON_PCM = E_INT_FIQ_0x20_START+12, 178 E_INT_FIQ_EMAC = E_INT_FIQ_0x20_START+13, 179 E_INT_FIQ_SE_DSP2UP = E_INT_FIQ_0x20_START+14, 180 E_INT_FIQ_TSP2AEON = E_INT_FIQ_0x20_START+15, 181 E_INT_FIQ_0x20_END = 0x2F, 182 183 E_INT_FIQ_0x30_START = 0x30, 184 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0, 185 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1, 186 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2, 187 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3, 188 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4, 189 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5, 190 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6, 191 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7, 192 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8, 193 E_INT_FIQ_INT_CCFL = E_INT_FIQ_0x30_START+9, 194 E_INT_FIQ_INT = E_INT_FIQ_0x30_START+10, 195 E_INT_FIQ_IR = E_INT_FIQ_0x30_START+11, 196 E_INT_FIQ_AFEC_VSYNC = E_INT_FIQ_0x30_START+12, 197 E_INT_FIQ_DEC_DSP2UP = E_INT_FIQ_0x30_START+13, 198 E_INT_FIQ_MIPS_WDT = E_INT_FIQ_0x30_START+14, //U3 199 E_INT_FIQ_DEC_DSP2MIPS = E_INT_FIQ_0x30_START+15, 200 E_INT_FIQ_0x30_END = 0x3F, 201 202 E_INT_IRQ_0x40_START = 0x40, 203 E_INT_IRQ_SVD_HVD = E_INT_IRQ_0x40_START+0, 204 E_INT_IRQ_USB2 = E_INT_IRQ_0x40_START+1, 205 E_INT_IRQ_UHC2 = E_INT_IRQ_0x40_START+2, 206 E_INT_IRQ_MIU = E_INT_IRQ_0x40_START+3, 207 E_INT_IRQ_GDMA = E_INT_IRQ_0x40_START+4, //U3 208 E_INT_IRQ_UART2 = E_INT_IRQ_0x40_START+5, //U3 209 E_INT_IRQ_UART1 = E_INT_IRQ_0x40_START+6, //U3 210 E_INT_IRQ_DEMOD = E_INT_IRQ_0x40_START+7, //U3 211 E_INT_IRQ_MPIF = E_INT_IRQ_0x40_START+8, //U3 212 E_INT_IRQ_JPD = E_INT_IRQ_0x40_START+9, //U3 213 E_INT_IRQ_AEON2HI = E_INT_IRQ_0x40_START+10, //U3 214 E_INT_IRQ_BDMA0 = E_INT_IRQ_0x40_START+11, //U3 215 E_INT_IRQ_BDMA1 = E_INT_IRQ_0x40_START+12, //U3 216 E_INT_IRQ_OTG = E_INT_IRQ_0x40_START+13, //U3 217 E_INT_IRQ_MVD_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+14, //U3 218 E_INT_IRQ_TSP_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+15, //U3 219 E_INT_IRQ_0x40_END = 0x4F, 220 221 E_INT_IRQ_0x50_START = 0x50, 222 E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0, //U3 223 E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1, //U3 224 E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2, //U3 225 E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3, //U3 226 E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4, //U3 227 E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5, //U3 228 E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6, //U3 229 E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7, //U3 230 E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8, //U3 231 E_INT_IRQ_DMA_WADR_ERR = E_INT_IRQ_0x50_START+9, //U3 232 E_INT_IRQ_UP_IRQ_UART_CA = E_INT_IRQ_0x50_START+10, //U3 233 E_INT_IRQ_UP_IRQ_EMM_ECM = E_INT_IRQ_0x50_START+11, //U3 234 E_INT_IRQ_ONIF = E_INT_IRQ_0x50_START+12, //T8 235 E_INT_IRQ_USB1 = E_INT_IRQ_0x50_START+13, //T8 236 E_INT_IRQ_UHC1 = E_INT_IRQ_0x50_START+14, //T8 237 E_INT_IRQ_MFE = E_INT_IRQ_0x50_START+15, //T8 238 E_INT_IRQ_0x50_END = 0x5F, 239 240 E_INT_FIQ_0x60_START = 0x60, 241 E_INT_FIQ_IR_INT_RC = E_INT_FIQ_0x60_START+0, //U3 242 E_INT_FIQ_HDMITX_IRQ_EDGE = E_INT_FIQ_0x60_START+1, //U3 243 E_INT_FIQ_UP_IRQ_UART_CA = E_INT_FIQ_0x60_START+2, //U3 244 E_INT_FIQ_UP_IRQ_EMM_ECM = E_INT_FIQ_0x60_START+3, //U3 245 E_INT_FIQ_PVR2MI_INT0 = E_INT_FIQ_0x60_START+4, //U3 246 E_INT_IRQ_CA_RSA_INT0 = E_INT_FIQ_0x60_START+4, //Keltic / Kaiser / keres 247 E_INT_FIQ_PVR2MI_INT1 = E_INT_FIQ_0x60_START+5, //U3 248 E_INT_IRQ_FIQ_INT = E_INT_FIQ_0x60_START+6, //Kappa 249 E_INT_IRQ_UART3 = E_INT_FIQ_0x60_START+7, //Kappa 250 E_INT_FIQ_AEON_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+8, //T3, 251 E_INT_FIQ_AEON_TO_MIPS_VPE1 = E_INT_FIQ_0x60_START+9, //T3, E_INT_FIQ_AEON_TO_BEON 252 E_INT_FIQ_SECEMAC = E_INT_FIQ_0x60_START+10, //Kaiser 253 E_INT_FIQ_IR2_INT = E_INT_FIQ_0x60_START+11, //Kaiser 254 E_INT_FIQ_MIPS_VPE1_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+12, //T3 255 E_INT_FIQ_MIPS_VPE1_TO_AEON = E_INT_FIQ_0x60_START+13, //T3 256 E_INT_FIQ_MIPS_VPE1_TO_8051 = E_INT_FIQ_0x60_START+14, //T3 257 E_INT_FIQ_IR2_INT_RC = E_INT_FIQ_0x60_START+15, //Kaiser 258 E_INT_FIQ_0x60_END = 0x6F, 259 260 E_INT_FIQ_0x70_START = 0x70, 261 E_INT_FIQ_MIPS_VPE0_TO_MIPS_VPE1 = E_INT_FIQ_0x70_START+0, //T3 262 E_INT_FIQ_MIPS_VPE0_TO_AEON = E_INT_FIQ_0x70_START+1, //T3, E_INT_FIQ_AEON_TO_BEON 263 E_INT_FIQ_MIPS_VPE0_TO_8051 = E_INT_FIQ_0x70_START+2, //T3, E_INT_FIQ_BEON_TO_8051 264 E_INT_FIQ_IR_IN = E_INT_FIQ_0x70_START+3, //T8 265 E_INT_FIQ_DMDMCU2HK = E_INT_FIQ_0x70_START+4, 266 E_INT_FIQ_R2TOMCU_INT0 = E_INT_FIQ_0x70_START+5, //T8 267 E_INT_FIQ_R2TOMCU_INT1 = E_INT_FIQ_0x70_START+6, //T8 268 E_INT_FIQ_DSPTOMCU_INT0 = E_INT_FIQ_0x70_START+7, //T8 269 E_INT_FIQ_DSPTOMCU_INT1 = E_INT_FIQ_0x70_START+8, //T8 270 E_INT_FIQ_USB = E_INT_FIQ_0x70_START+9, //T8 271 E_INT_FIQ_UHC = E_INT_FIQ_0x70_START+10, //T8 272 E_INT_FIQ_USB1 = E_INT_FIQ_0x70_START+11, //T8 273 E_INT_FIQ_UHC1 = E_INT_FIQ_0x70_START+12, //T8 274 E_INT_FIQ_USB2 = E_INT_FIQ_0x70_START+13, //T8 275 E_INT_FIQ_UHC2 = E_INT_FIQ_0x70_START+14, //T8 276 //Not Used = E_INT_FIQ_0x70_START+15, 277 E_INT_FIQ_0x70_END = 0x7F, 278 279 280 // Add IRQ from 0x80 ~ 0xBF, 281 // if IRQ enum from 0x00 ~ 0x1F, and 0x40 ~ 0x5F is occupied 282 E_INT_IRQ_0x80_START = 0x80, 283 E_INT_IRQ_MLINK = E_INT_IRQ_0x80_START+0, //U3 284 E_INT_IRQ_AFEC = E_INT_IRQ_0x80_START+1, //T3 285 E_INT_IRQ_DPTX = E_INT_IRQ_0x80_START+2, //T3 286 E_INT_IRQ_TMDDRLINK = E_INT_IRQ_0x80_START+3, //T3 287 E_INT_IRQ_DISPI = E_INT_IRQ_0x80_START+4, //T3 288 E_INT_IRQ_EXP_MLINK = E_INT_IRQ_0x80_START+5, //T3 289 E_INT_IRQ_M4VE = E_INT_IRQ_0x80_START+6, //T3 290 E_INT_IRQ_DVI_HDMI_HDCP = E_INT_IRQ_0x80_START+7, //T3 291 E_INT_IRQ_G3D2MCU = E_INT_IRQ_0x80_START+8, //T3 292 E_INT_IRQ_VP6 = E_INT_IRQ_0x80_START+9, //A3 293 E_INT_IRQ_INT = E_INT_IRQ_0x80_START+10, //M12 294 E_INT_IRQ_CEC = E_INT_IRQ_0x80_START+11, //T8 295 E_INT_IRQ_HDCP_IIC = E_INT_IRQ_0x80_START+12, //T8 296 E_INT_IRQ_HDCP_X74 = E_INT_IRQ_0x80_START+13, //T8 297 E_INT_IRQ_WADR_ERR = E_INT_IRQ_0x80_START+14, //T8 298 E_INT_IRQ_DCSUB = E_INT_IRQ_0x80_START+15, //T8 299 E_INT_IRQ_0x80_END = 0x8F, 300 301 E_INT_IRQ_0x90_START = 0x90, 302 E_INT_IRQ_GE = E_INT_IRQ_0x90_START+0, //T8 303 E_INT_IRQ_SYNC_DET = E_INT_IRQ_0x90_START+1, //M10 304 E_INT_IRQ_FSP = E_INT_IRQ_0x90_START+2, //M10 305 E_INT_IRQ_PWM_RP_L = E_INT_IRQ_0x90_START+3, //M10 306 E_INT_IRQ_PWM_FP_L = E_INT_IRQ_0x90_START+4, //M10 307 E_INT_IRQ_PWM_RP_R = E_INT_IRQ_0x90_START+5, //M10 308 E_INT_IRQ_PWM_FP_R = E_INT_IRQ_0x90_START+6, //M10 309 E_INT_IRQ_FRC_SC = E_INT_IRQ_0x90_START+7, //A5 310 E_INT_IRQ_FRC_INT_FIQ2HST0 = E_INT_IRQ_0x90_START+8, //A5 311 E_INT_IRQ_SMART = E_INT_IRQ_0x90_START+9, //A5 312 E_INT_IRQ_MVD2MIPS = E_INT_IRQ_0x90_START+10, //A5 313 E_INT_IRQ_GPD = E_INT_IRQ_0x90_START+11, //A5 314 E_INT_IRQ_DS = E_INT_IRQ_0x90_START+12, //Kappa 315 E_INT_IRQ_FRC_INT_IRQ2HST0 = E_INT_IRQ_0x90_START+13, //A5 316 E_INT_IRQ_MIIC_DMA_INT3 = E_INT_IRQ_0x90_START+14, //A5 317 E_INT_IRQ_MIIC_INT3 = E_INT_IRQ_0x90_START+15, //A5 318 E_INT_IRQ_0x90_END = 0x9F, 319 320 E_INT_IRQ_0xA0_START = 0xA0, 321 E_INT_IRQ_IIC2 = E_INT_IRQ_0xA0_START+0, //A1 322 E_INT_IRQ_MIIC_DMA0 = E_INT_IRQ_0xA0_START+1, //A1 323 E_INT_IRQ_MIIC_DMA1 = E_INT_IRQ_0xA0_START+2, //A1 324 E_INT_IRQ_MIIC_DMA2 = E_INT_IRQ_0xA0_START+3, //A1 325 E_INT_IRQ_MSPI0 = E_INT_IRQ_0xA0_START+4, //A1 326 E_INT_IRQ_MSPI1 = E_INT_IRQ_0xA0_START+5, //A1 327 E_INT_IRQ_EXT_GPIO0 = E_INT_IRQ_0xA0_START+6, //A1 328 E_INT_IRQ_EXT_GPIO1 = E_INT_IRQ_0xA0_START+7, //A1 329 E_INT_IRQ_EXT_GPIO2 = E_INT_IRQ_0xA0_START+8, //A1 330 E_INT_IRQ_EXT_GPIO3 = E_INT_IRQ_0xA0_START+9, //A1 331 E_INT_IRQ_EXT_GPIO4 = E_INT_IRQ_0xA0_START+10, //A1 332 E_INT_IRQ_EXT_GPIO5 = E_INT_IRQ_0xA0_START+11, //A1 333 E_INT_IRQ_EXT_GPIO6 = E_INT_IRQ_0xA0_START+12, //A1 334 E_INT_IRQ_EXT_GPIO7 = E_INT_IRQ_0xA0_START+13, //A1 335 E_INT_IRQ_MIIC_DMA_INT2 = E_INT_IRQ_0xA0_START+14, //A5 336 E_INT_IRQ_MIIC_INT2 = E_INT_IRQ_0xA0_START+15, //A5 337 E_INT_IRQ_0xA0_END = 0xAF, 338 339 E_INT_IRQ_0xB0_START = 0xB0, 340 E_INT_IRQ_MIIC_DMA_INT1 = E_INT_IRQ_0xB0_START+0, //A5 341 E_INT_IRQ_MIIC_INT1 = E_INT_IRQ_0xB0_START+1, //A5 342 E_INT_IRQ_MIIC_DMA_INT0 = E_INT_IRQ_0xB0_START+2, //A5 343 E_INT_IRQ_MIIC_INT0 = E_INT_IRQ_0xB0_START+3, //A5 344 E_INT_IRQ_UHC30 = E_INT_IRQ_0xB0_START+4, //Agate 345 E_INT_IRQ_AU_DMA = E_INT_IRQ_0xB0_START+5, //Agate 346 E_INT_IRQ_DIPW = E_INT_IRQ_0xB0_START+6, //Agate 347 E_INT_IRQ_HDMITX = E_INT_IRQ_0xB0_START+7, //Agate 348 E_INT_IRQ_U3_DPHY = E_INT_IRQ_0xB0_START+8, //Agate 349 E_INT_IRQEXPL_TSO = E_INT_IRQ_0xB0_START+9, //Agate 350 E_INT_IRQ_TSP_TSO0 = E_INT_IRQ_0xB0_START+9, //Keltic , Kiaser Add 351 E_INT_IRQEXPH_CEC1 = E_INT_IRQ_0xB0_START+10, //Agate 352 E_INT_IRQ_TSP_TSO1 = E_INT_IRQ_0xB0_START+10, //Keltic , Kiaser Add 353 E_INT_IRQ_BT_DMA = E_INT_IRQ_0xB0_START+11, //Kaiser 354 E_INT_IRQ_BT_TAB = E_INT_IRQ_0xB0_START+12, //Kaiser 355 E_INT_IRQ_SATA = E_INT_IRQ_0xB0_START+13, //Kaiser 356 E_INT_IRQ_MHL_CBUS_PM = E_INT_IRQ_0xB0_START+14, //Emerald, Eden 357 E_INT_IRQ_MHL_CBUS_WAKEUP = E_INT_IRQ_0xB0_START+15, //Eden 358 E_INT_IRQ_0xB0_END = 0xBF, 359 360 361 // Add FIQ from 0xC0 ~ 0xFD, 362 // if FIQ enum from 0x20 ~ 0x4F, and 0x60 ~ 0x7F is occupied 363 E_INT_FIQ_0xC0_START = 0xC0, 364 E_INT_FIQ_DMARD = E_INT_FIQ_0xC0_START+0, //U3 365 E_INT_FIQ_AU_DMA_BUF_INT = E_INT_FIQ_0xC0_START+1, //T3 366 E_INT_FIQ_8051_TO_MIPS_VPE1 = E_INT_FIQ_0xC0_START+2, //T3 367 E_INT_FIQ_DVI_DET = E_INT_FIQ_0xC0_START+3, //M10 368 E_INT_FIQ_PM_GPIO0 = E_INT_FIQ_0xC0_START+4, //M10 369 E_INT_FIQ_PM_GPIO1 = E_INT_FIQ_0xC0_START+5, //M10 370 E_INT_FIQ_PM_GPIO2 = E_INT_FIQ_0xC0_START+6, //M10 371 E_INT_FIQ_PM_GPIO3 = E_INT_FIQ_0xC0_START+7, //M10 372 E_INT_FIQ_PM_XIU_TIMEOUT = E_INT_FIQ_0xC0_START+8, //M10 373 E_INT_FIQ_PWM_RP_RP_L = E_INT_FIQ_0xC0_START+9, //M10 374 E_INT_FIQ_PWM_RP_FP_L = E_INT_FIQ_0xC0_START+10, //M10 375 E_INT_FIQ_PWM_RP_RP_R = E_INT_FIQ_0xC0_START+11, //M10 376 E_INT_FIQ_PWM_RP_FP_R = E_INT_FIQ_0xC0_START+12, //M10 377 E_INT_FIQ_8051_TO_MIPS_VPE0 = E_INT_FIQ_0xC0_START+13, //A5 378 E_INT_FIQ_FRC_R2_TO_MIPS = E_INT_FIQ_0xC0_START+14, 379 E_INT_FIQ_VP6 = E_INT_FIQ_0xC0_START+15, //A3 380 E_INT_FIQ_0xC0_END = 0xCF, 381 382 E_INT_FIQ_0xD0_START = 0xD0, 383 E_INT_FIQ_STRETCH = E_INT_FIQ_0xD0_START+0, 384 E_INT_FIQ_GPIO0 = E_INT_FIQ_0xD0_START+1, //T12 385 E_INT_FIQ_GPIO1 = E_INT_FIQ_0xD0_START+2, //T12 386 E_INT_FIQ_GPIO2 = E_INT_FIQ_0xD0_START+3, //T12 387 E_INT_FIQ_GPIO3 = E_INT_FIQ_0xD0_START+4, //T12 388 E_INT_FIQ_GPIO4 = E_INT_FIQ_0xD0_START+5, //T12 389 E_INT_FIQ_GPIO5 = E_INT_FIQ_0xD0_START+6, //T12 390 E_INT_FIQ_GPIO6 = E_INT_FIQ_0xD0_START+7, //T12 391 E_INT_FIQ_GPIO7 = E_INT_FIQ_0xD0_START+8, //T12 392 E_INT_FIQ_VE_VSYNC_IN = E_INT_FIQ_0xD0_START+9, //Agate 393 E_INT_FIQEXPL_HST0_TO_3 = E_INT_FIQ_0xD0_START+10, //Agate 394 E_INT_FIQEXPL_HST1_TO_3 = E_INT_FIQ_0xD0_START+11, //Agate 395 E_INT_FIQEXPL_HST2_TO_3 = E_INT_FIQ_0xD0_START+12, //Agate 396 E_INT_FIQEXPH_CMDQ = E_INT_FIQ_0xD0_START+13, //Agate 397 E_INT_FIQEXPH_HDMITX_EDGE = E_INT_FIQ_0xD0_START+14, //Agate 398 E_INT_FIQEXPH_UHC30 = E_INT_FIQ_0xD0_START+15, //Agate 399 E_INT_INT_FIQ_0xD0_END = 0xDF, 400 401 E_INT_FIQ_0xE0_START = 0xE0, 402 E_INT_FIQ_LDM_DMA0 = E_INT_FIQ_0xE0_START+0, //A1 403 E_INT_IRQ_RASP1 = E_INT_FIQ_0xE0_START+0, //Kaiser 404 E_INT_FIQ_LDM_DMA1 = E_INT_FIQ_0xE0_START+1, //A1 405 E_INT_IRQ_SECEMAC = E_INT_FIQ_0xE0_START+1, //Kaiser 406 E_INT_IRQ_SDIO = E_INT_FIQ_0xE0_START+2, //K2 407 E_INT_IRQ_UHC3 = E_INT_FIQ_0xE0_START+3, //K2 408 E_INT_IRQ_USB3 = E_INT_FIQ_0xE0_START+4, //K2 409 E_INT_FIQ_GPIO8 = E_INT_FIQ_0xE0_START+5, //Eagle 410 E_INT_FIQ_GPIO9 = E_INT_FIQ_0xE0_START+6, //Eagle 411 E_INT_FIQ_DISP_TGEN0 = E_INT_FIQ_0xE0_START+7, //Eagle 412 E_INT_FIQ_CA_CRYPTO_DMA = E_INT_FIQ_0xE0_START+7, //Keltic , Kaiser Add 413 E_INT_FIQ_DISP_TGEN1 = E_INT_FIQ_0xE0_START+8, //Eagle 414 E_INT_IRQ_CA_PROG_PVR = E_INT_FIQ_0xE0_START+8, //Keltic , Kaiser Add 415 E_INT_FIQ_DISP_TGEN2 = E_INT_FIQ_0xE0_START+9, //Eagle 416 E_INT_IRQ_CA_NSK_INT = E_INT_FIQ_0xE0_START+9, //Keltic , Kaiser Add 417 E_INT_FIQ_DISP_TGEN3 = E_INT_FIQ_0xE0_START+10, //Eagle 418 E_INT_IRQ_TSP_ECM_FLT = E_INT_FIQ_0xE0_START+10, //Kaiser 419 E_INT_IRQ_ERROR_RESP = E_INT_FIQ_0xE0_START+11, //Edison 420 E_INT_IRQ_MIU_SECURITY = E_INT_FIQ_0xE0_START+12, //Edison 421 E_INT_FIQ_TEMPERATURE_FLAG_FALL = E_INT_FIQ_0xE0_START+13, //Eiffel 422 E_INT_IRQ_DISP1 = E_INT_FIQ_0xE0_START+13, //Kaiser 423 E_INT_FIQ_TEMPERATURE_FLAG_RISE = E_INT_FIQ_0xE0_START+14, //Eiffel 424 E_INT_IRQ_RTC1 = E_INT_FIQ_0xE0_START+14, //Kaiser 425 E_INT_FIQ_U3_DPHY = E_INT_FIQ_0xE0_START+15, //Eiffel 426 E_INT_IRQ_GPU2MCU = E_INT_FIQ_0xE0_START+15, //Kaiser 427 E_INT_FIQ_0xE0_END = 0xEF, 428 429 E_INT_FIQ_0xF0_START = 0xF0, 430 E_INT_FIQ_DEC_DSP2R2M = E_INT_FIQ_0xF0_START+0, 431 E_INT_FIQ_AEON_TO_R2M = E_INT_FIQ_0xF0_START+1, 432 E_INT_FIQ_R2M_TO_AEON = E_INT_FIQ_0xF0_START+2, 433 E_INT_FIQ_R2M_TO_8051 = E_INT_FIQ_0xF0_START+3, 434 E_INT_IRQ_VIVALDI_DMA_INTR2 = E_INT_FIQ_0xF0_START+4, 435 E_INT_FIQ_AU_DMA_INT = E_INT_FIQ_0xF0_START+4, //Kaiser 436 E_INT_IRQ_VIVALDI_DMA_INTR1 = E_INT_FIQ_0xF0_START+5, 437 E_INT_FIQ_AU_PCM_DMA_INT = E_INT_FIQ_0xF0_START+5, //Kaiser 438 E_INT_IRQ_AFEC_INT = E_INT_FIQ_0xF0_START+6, 439 E_INT_FIQ_AU_SPDIF_TX_CS0 = E_INT_FIQ_0xF0_START + 7, 440 E_INT_FIQ_AU_SPDIF_TX_CS1 = E_INT_FIQ_0xF0_START + 8, //Eiffel 441 E_INT_FIQ_PCM_DMA = E_INT_FIQ_0xF0_START + 9, //Eiffel 442 E_INT_FIQ_DMDMCU2HK_1 = E_INT_FIQ_0xF0_START+9, //Kaiser 443 E_INT_FIQ_VE_SW_WR2BUF = E_INT_FIQ_0xF0_START+10, //Kaiser 444 E_INT_IRQ_FRM_PM = E_INT_FIQ_0xF0_START+11, 445 E_INT_FIQ_FRM_PM = E_INT_FIQ_0xF0_START+12, 446 E_INT_FIQ_SATA_PHY = E_INT_FIQ_0xF0_START+13, 447 E_INT_IRQ_FIQ_NONE = E_INT_FIQ_0xF0_START+14, 448 E_INT_IRQ_FIQ_ALL = E_INT_FIQ_0xF0_START+15, 449 E_INT_FIQ_0xF0_END = 0xFF, 450 451 E_INT_IRQ_0x100_START = 0x100, 452 E_INT_IRQ_RIU_ERROR = E_INT_IRQ_0x100_START+0, //Nugget 453 E_INT_IRQ_EVD = E_INT_IRQ_0x100_START+1, //Einstein 454 E_INT_IRQ_SWCD = E_INT_IRQ_0x100_START+1, //Nugget 455 E_INT_IRQ_MIU_SECURE = E_INT_IRQ_0x100_START+2, //Nugget 456 E_INT_IRQ_TIMER2 = E_INT_IRQ_0x100_START+3, //Nugget 457 E_INT_FIQ_8051_TO_SECURER2 = E_INT_IRQ_0x100_START+4, //Nugget 458 E_INT_FIQ_AEON_TO_SECURER2 = E_INT_IRQ_0x100_START+5, //Nugget 459 E_INT_FIQ_BEON_TO_SECURER2 = E_INT_IRQ_0x100_START+6, //Nugget 460 E_INT_FIQ_SECURER2_TO_BEON = E_INT_IRQ_0x100_START+7, //Nugget 461 E_INT_FIQ_SECURER2_TO_AEON = E_INT_IRQ_0x100_START+8, //Nugget 462 E_INT_FIQ_SECURER2_TO_8051 = E_INT_IRQ_0x100_START+9, //Nugget 463 E_INT_IRQ_SAR1 = E_INT_IRQ_0x100_START+10, //keres 464 E_INT_IRQ_IDAC_PLUG_DET = E_INT_IRQ_0x100_START+11, //keres 465 E_INT_FIQ_AU_SPDIF_TX_CS2 = E_INT_IRQ_0x100_START+12, //keres 466 E_INT_IRQ_CA_IP_INT = E_INT_IRQ_0x100_START+13, //keres 467 E_INT_IRQ_AKL_INT = E_INT_IRQ_0x100_START+14, //keres 468 E_INT_FIQ_MB_A2M_INT0 = E_INT_IRQ_0x100_START+15, //keres 469 E_INT_FIQ_0x100_END = 0x10F, 470 471 E_INT_FIQ_0x110_START = 0x110, 472 E_INT_FIQ_MB_D2M_INT0 = E_INT_FIQ_0x110_START+0, //keres 473 E_INT_FIQ_MB_D2M_INT1 = E_INT_FIQ_0x110_START+1, //keres 474 E_INT_FIQ_MB_A2M_INT1 = E_INT_FIQ_0x110_START+2, //keres 475 E_INT_FIQ_MB_A2M_INT2 = E_INT_FIQ_0x110_START+3, //keres 476 E_INT_FIQ_MB_A2M_INT3 = E_INT_FIQ_0x110_START+4, //keres 477 E_INT_IRQ_FIQ_OTG = E_INT_FIQ_0x110_START+5, //clippers 478 E_INT_IRQ_VP9_HK2VD_R2 = E_INT_FIQ_0x110_START+6, //maonco vp9_hk2vd_r2_int 479 E_INT_FIQ_8051_TO_SECURE51 = E_INT_FIQ_0x110_START+7, //keres 480 E_INT_FIQ_SECURE51_TO_8051 = E_INT_FIQ_0x110_START+8, //keres 481 E_INT_FIQ_BEON_TO_SECURE51 = E_INT_FIQ_0x110_START+9, //keres 482 E_INT_FIQ_SECURE51_TO_BEON = E_INT_FIQ_0x110_START+10, //keres 483 E_INT_FIQ_SECURER2_TO_SECURE51 = E_INT_FIQ_0x110_START+11, //keres 484 E_INT_FIQ_SECURE51_TO_SECURER2 = E_INT_FIQ_0x110_START+12, //keres 485 E_INT_FIQ_PM_SD_CDZ0 = E_INT_FIQ_0x110_START + 13, //Miami 486 E_INT_FIQ_PM_SD_CDZ1 = E_INT_FIQ_0x110_START + 14, //Miami 487 E_INT_FIQ_0x110_END = 0x11F, 488 489 E_INT_IRQ_0x120_START = 0x120, 490 E_INT_IRQ_USB30_SS_INT = E_INT_IRQ_0x120_START + 1, //Miami 491 E_INT_IRQ_USB30_HS_UHC_INT0 = E_INT_IRQ_0x120_START + 2, //Miami 492 E_INT_IRQ_USB30_HS_UHC_INT1 = E_INT_IRQ_0x120_START + 3, //Miami 493 E_INT_IRQ_USB30_HS_USB_INT = E_INT_IRQ_0x120_START + 4, //Miami 494 E_INT_IRQ_MIIC_INT4 = E_INT_IRQ_0x120_START + 5, //Miami 495 E_INT_IRQ_MIIC_INT5 = E_INT_IRQ_0x120_START + 6, //Miami 496 E_INT_IRQ_UART4 = E_INT_IRQ_0x120_START + 7, //Miami 497 E_INT_IRQ_BDMA = E_INT_IRQ_0x120_START + 8, //Miami 498 E_INT_IRQ_ZDEC = E_INT_IRQ_0x120_START + 9, //Miami 499 E_INT_IRQ_FRC = E_INT_IRQ_0x120_START + 10, //Miami 500 E_INT_FIQ_USB3 = E_INT_IRQ_0x120_START + 11, //Miami 501 E_INT_FIQ_UHC3 = E_INT_IRQ_0x120_START + 12, //Miami 502 E_INT_FIQ_R2TOMCU_INT2 = E_INT_IRQ_0x120_START + 13, //Miami 503 E_INT_FIQ_R2TOMCU_INT3 = E_INT_IRQ_0x120_START + 14, //Miami 504 E_INT_IRQ_0x120_END = 0x12F, 505 506 E_INT_IRQ_0x130_START = 0x130, 507 E_INT_IRQ_AUDMA_V2_INT = E_INT_IRQ_0x130_START + 1, //Muji 508 E_INT_IRQ_EMMC_OSP_INT = E_INT_IRQ_0x130_START + 2, //Muji 509 E_INT_IRQ_MHL_ECBUS_INT = E_INT_IRQ_0x130_START + 3, //Muji 510 E_INT_IRQ_SDIO_OSP_INT = E_INT_IRQ_0x130_START + 4, //Muji 511 E_INT_IRQ_DISP_FE_INT = E_INT_IRQ_0x130_START + 7, //Manhattan 512 E_INT_IRQ_SCDC_PM_INT = E_INT_IRQ_0x130_START + 8, //Manhattan 513 E_INT_IRQ_USB30_HS1_USB_INT = E_INT_IRQ_0x130_START + 9, //Manhattan 514 E_INT_IRQ_USB30_HS1_UHC_INT = E_INT_IRQ_0x130_START + 10, //Manhattan 515 E_INT_IRQ_USB30_HS_UHC_INT = E_INT_IRQ_0x130_START + 11, //Manhattan 516 E_INT_IRQ_TSP_FI_QUEUE_INT = E_INT_IRQ_0x130_START + 12, //Manhattan 517 E_INT_IRQ_DISP_SC2_INT = E_INT_IRQ_0x130_START + 13, //Manhattan 518 E_INT_IRQ_MSPI_MCARD_INT = E_INT_IRQ_0x130_START + 14, //Manhattan 519 E_INT_IRQ_CFKTKS_NONSEC_INT = E_INT_IRQ_0x130_START + 15, //Manhattan 520 E_INT_IRQ_0x130_END = 0x13F, 521 522 E_INT_IRQ_0x140_START = 0x140, 523 E_INT_IRQ_CFKTKS_INT = E_INT_IRQ_0x140_START + 0, //Manhattan 524 E_INT_IRQ_CFDONE_INT = E_INT_IRQ_0x140_START + 1, //Manhattan 525 E_INT_IRQ_MIU_TLB_INT = E_INT_IRQ_0x140_START + 2, //Manhattan 526 E_INT_IRQ_PAS_PTS_COMBINE_INT = E_INT_IRQ_0x140_START + 3, //Manhattan 527 E_INT_IRQ_AESDMA_S_INT = E_INT_IRQ_0x140_START + 4, //Manhattan 528 E_INT_IRQ_VD_EVD_R22HI_INT = E_INT_IRQ_0x140_START + 5, //Manhattan 529 E_INT_IRQ_0x140_END = 0x14F, 530 531 E_INT_FIQ_0x150_START = 0x150, 532 E_INT_FIQ_LAN_ESD_INT = E_INT_FIQ_0x150_START + 0, //Manhattan 533 E_INT_FIQ_TIMER2_INT = E_INT_FIQ_0x150_START + 1, //Manhattan 534 E_INT_FIQ_0x150_END = 0x15F, 535 536 } InterruptNum; 537 538 typedef enum 539 { 540 // IRQ 541 E_FRCINT_IRQ_0x00_START = 0x00, 542 E_FRCINT_IRQ_ERROR_RESP_INT = E_FRCINT_IRQ_0x00_START+ 6, //manhattan 543 E_FRCINT_IRQ_MC2D_MEDONE_INT3 = E_FRCINT_IRQ_0x00_START+ 7, //manhattan 544 E_FRCINT_IRQ_MC2D_MEDONE_INT2 = E_FRCINT_IRQ_0x00_START+ 8, //manhattan 545 E_FRCINT_IRQ_MC2D_MEDONE_INT1 = E_FRCINT_IRQ_0x00_START+ 9, //manhattan 546 E_FRCINT_IRQ_MC2D_MEDONE_INT0 = E_FRCINT_IRQ_0x00_START+10, //manhattan 547 E_FRCINT_IRQ_FSC_INT1 = E_FRCINT_IRQ_0x00_START+11, //manhattan 548 E_FRCINT_IRQ_FSC_INT0 = E_FRCINT_IRQ_0x00_START+12, //manhattan 549 E_FRCINT_IRQ_0x00_END = 0x0F, 550 551 E_FRCINT_IRQ_0x10_START = 0x10, 552 E_FRCINT_IRQ_FRC_XIU_TIMEOUT = E_FRCINT_IRQ_0x10_START+5, 553 E_FRCINT_IRQ_PWM_RP_L = E_FRCINT_IRQ_0x10_START+6, 554 E_FRCINT_IRQ_PWM_FP_L = E_FRCINT_IRQ_0x10_START+7, 555 E_FRCINT_IRQ_PWM_RP_R = E_FRCINT_IRQ_0x10_START+8, 556 E_FRCINT_IRQ_PWM_FP_R = E_FRCINT_IRQ_0x10_START+9, 557 E_FRCINT_IRQ_SC = E_FRCINT_IRQ_0x10_START+10, 558 E_FRCINT_IRQ_D2B = E_FRCINT_IRQ_0x10_START+11, 559 E_FRCINT_IRQ_MSPI3 = E_FRCINT_IRQ_0x10_START+12, // agate 560 E_FRCINT_IRQ_MSPI2 = E_FRCINT_IRQ_0x10_START+13, // agate 561 E_FRCINT_IRQ_MSPI1 = E_FRCINT_IRQ_0x10_START+14, 562 E_FRCINT_IRQ_MSPI0 = E_FRCINT_IRQ_0x10_START+15, 563 E_FRCINT_IRQ_0x10_END = 0x1F, 564 565 // FIQ 566 E_FRCINT_FIQ_0x20_START = 0x20, 567 E_FRCINT_FIQ_HST0_TO_HST1 = E_FRCINT_FIQ_0x20_START+ 0, //manhattan 568 E_FRCINT_FIQ_HST0_TO_HST2 = E_FRCINT_FIQ_0x20_START+ 1, //manhattan 569 E_FRCINT_FIQ_HST0_TO_HST3 = E_FRCINT_FIQ_0x20_START+ 2, //manhattan 570 E_FRCINT_FIQ_HST1_TO_HST0 = E_FRCINT_FIQ_0x20_START+ 3, //manhattan 571 E_FRCINT_FIQ_HST1_TO_HST2 = E_FRCINT_FIQ_0x20_START+ 4, //manhattan 572 E_FRCINT_FIQ_HST1_TO_HST3 = E_FRCINT_FIQ_0x20_START+ 5, //manhattan 573 E_FRCINT_FIQ_HST2_TO_HST0 = E_FRCINT_FIQ_0x20_START+ 6, //manhattan 574 E_FRCINT_FIQ_HST2_TO_HST1 = E_FRCINT_FIQ_0x20_START+ 7, //manhattan 575 E_FRCINT_FIQ_HST2_TO_HST3 = E_FRCINT_FIQ_0x20_START+ 8, //manhattan 576 E_FRCINT_FIQ_HST3_TO_HST0 = E_FRCINT_FIQ_0x20_START+ 9, //manhattan 577 E_FRCINT_FIQ_HST3_TO_HST1 = E_FRCINT_FIQ_0x20_START+10, //manhattan 578 E_FRCINT_FIQ_HST3_TO_HST2 = E_FRCINT_FIQ_0x20_START+11, //manhattan 579 E_FRCINT_FIQ_FRC_TIMER0 = E_FRCINT_FIQ_0x20_START+12, //manhattan 580 E_FRCINT_FIQ_FRC_TIMER1 = E_FRCINT_FIQ_0x20_START+13, //manhattan 581 582 //Special definition for FRC 583 E_FRCINT_FIQ_HKCPU_TO_FRCR2 = E_FRCINT_FIQ_HST0_TO_HST1, 584 E_FRCINT_FIQ_FRCR2_TO_HKCPU = E_FRCINT_FIQ_HST1_TO_HST0, 585 E_FRCINT_FIQ_HKIPVS_TO_FRCR2 = E_FRCINT_FIQ_HST0_TO_HST2, 586 E_FRCINT_FIQ_HKOPVS_TO_FRCR2 = E_FRCINT_FIQ_HST0_TO_HST3, 587 588 E_FRCINT_FIQ_0x20_END = 0x2F, 589 590 E_FRCINT_FIQ_0x30_START = 0x30, 591 E_FRCINT_FIQ_FRC_XIU_TIMEOUT = E_FRCINT_FIQ_0x30_START+ 2, //manhattan 592 E_FRCINT_FIQ_FRC_TO_MCU = E_FRCINT_FIQ_0x30_START+ 4, //manhattan 593 E_FRCINT_FIQ_MCU_TO_FRC = E_FRCINT_FIQ_0x30_START+ 5, //manhattan 594 595 E_FRCINT_FIQ_PWM_RP_L = E_FRCINT_FIQ_0x30_START+ 6, 596 E_FRCINT_FIQ_PWM_FP_L = E_FRCINT_FIQ_0x30_START+ 7, 597 E_FRCINT_FIQ_PWM_RP_R = E_FRCINT_FIQ_0x30_START+ 8, 598 E_FRCINT_FIQ_PWM_FP_R = E_FRCINT_FIQ_0x30_START+ 9, 599 E_FRCINT_FIQ_LDM_DMA_DONE3 = E_FRCINT_FIQ_0x30_START+10, 600 E_FRCINT_FIQ_LDM_DMA_DONE2 = E_FRCINT_FIQ_0x30_START+11, 601 E_FRCINT_FIQ_LDM_DMA_DONE1 = E_FRCINT_FIQ_0x30_START+12, 602 E_FRCINT_FIQ_LDM_DMA_DONE0 = E_FRCINT_FIQ_0x30_START+13, 603 E_FRCINT_FIQ_SC = E_FRCINT_FIQ_0x30_START+14, 604 E_FRCINT_FIQ_OP2_VS = E_FRCINT_FIQ_0x30_START+15, 605 E_FRCINT_FIQ_0x30_END = 0x3F, 606 607 // END 608 E_FRCINT_FIQ_0xF0_START = 0xF0, 609 E_FRCINT_IRQ_FIQ_NONE = E_FRCINT_FIQ_0xF0_START+14, 610 E_FRCINT_IRQ_FIQ_ALL = E_FRCINT_FIQ_0xF0_START+15, 611 E_FRCINT_FIQ_0xF0_END = 0xFF, 612 613 } InterruptNum_Frc; 614 615 #ifdef __cplusplus 616 } 617 #endif 618 619 #endif // _MS_IRQ_H_ 620