Lines Matching refs:E_INT_FIQ_0x30_START
31326 E_INT_FIQ_0x30_START = 0x30,
31327 E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0,
31328 E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1,
31329 E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2,
31330 E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3,
31331 E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4,
31332 E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5,
31333 E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6,
31334 E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7,
31335 E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8,
31336 E_INT_FIQ_INT_CCFL = E_INT_FIQ_0x30_START+9,
31337 E_INT_FIQ_INT = E_INT_FIQ_0x30_START+10,
31338 E_INT_FIQ_IR = E_INT_FIQ_0x30_START+11,
31339 E_INT_FIQ_AFEC_VSYNC = E_INT_FIQ_0x30_START+12,
31340 E_INT_FIQ_DEC_DSP2UP = E_INT_FIQ_0x30_START+13,
31341 E_INT_FIQ_MIPS_WDT = E_INT_FIQ_0x30_START+14,
31342 E_INT_FIQ_DEC_DSP2MIPS = E_INT_FIQ_0x30_START+15,