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Searched refs:CLK_REG (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/graphic/hal/kastor/ge/
H A DhalGE.c1707 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1717 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
/utopia/UTPA2-700.0.x/modules/graphic/hal/messi/ge/
H A DhalGE.c1735 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1745 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/manhattan/ge/
H A DhalGE.c1708 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1718 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/mainz/ge/
H A DhalGE.c1735 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1745 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/macan/ge/
H A DhalGE.c1696 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1706 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7821/ge/
H A DhalGE.c1802 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1812 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/maxim/ge/
H A DhalGE.c1724 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1734 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/k6/ge/
H A DhalGE.c1753 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1763 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
/utopia/UTPA2-700.0.x/modules/graphic/hal/M7621/ge/
H A DhalGE.c1724 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1734 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
/utopia/UTPA2-700.0.x/modules/graphic/hal/curry/ge/
H A DhalGE.c1707 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1717 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/kano/ge/
H A DhalGE.c1714 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1724 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/k6lite/ge/
H A DhalGE.c1750 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1760 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h139 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/maserati/ge/
H A DhalGE.c1802 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1812 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro
/utopia/UTPA2-700.0.x/modules/graphic/hal/mooney/ge/
H A DhalGE.c1742 u16tmp = CLK_REG(CHIP_GE_CLK); in GE_SetClock()
1752 CLK_REG(CHIP_GE_CLK) = u16tmp; in GE_SetClock()
H A DregGE.h140 #define CLK_REG(addr) RIU[ (((addr)*2) + 0x0B00UL)] macro

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