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Searched refs:CKG_OSDC_GATED (Results 1 – 21 of 21) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h620 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h620 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h915 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h921 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h914 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h908 #define CKG_OSDC_GATED BIT(0) macro
H A Dmhal_xc_chip_config.h.0907 #define CKG_OSDC_GATED BIT(0)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h787 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h894 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h855 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h906 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h841 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h911 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h898 #define CKG_OSDC_GATED BIT(0) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c5809 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
5814 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
5942 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c6452 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6457 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6585 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c6532 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6537 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6665 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c6979 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
6984 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7112 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c6999 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7004 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7132 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c7277 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7282 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7410 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c7277 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7282 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock in MHAL_SC_enable_osdc()
7410 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED)); in MHAL_SC_get_osdc_onoff_status()