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Searched refs:CKG_FMCLK_MASK (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c2252 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2258 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2263 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c2232 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2238 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2243 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c2319 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2325 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2330 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c6326 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c2495 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2501 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
2506 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7087 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c3131 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3137 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3142 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c3082 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3088 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3093 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7617 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c3133 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3139 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3144 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c3086 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3092 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3097 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
H A Dmhal_sc.c7640 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dmhal_xc_chip_config.h642 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dmhal_xc_chip_config.h648 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dmhal_xc_chip_config.h648 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h650 #define CKG_FMCLK_MASK BMASK(3:2) macro
H A Dmhal_xc_chip_config.h.0649 #define CKG_FMCLK_MASK BMASK(3:2)
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dmhal_xc_chip_config.h624 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dmhal_xc_chip_config.h724 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dmhal_xc_chip_config.h684 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dmhal_xc_chip_config.h736 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dmhal_xc_chip_config.h674 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dmhal_xc_chip_config.h741 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dmhal_xc_chip_config.h728 #define CKG_FMCLK_MASK BMASK(3:2) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c7049 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK); in Hal_SC_set_fmclk()

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