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Searched refs:ver_virstride (Results 1 – 13 of 13) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu383.c371 RK_U32 ver_virstride = 0; in fill_registers() local
376 ver_virstride = mpp_frame_get_ver_stride(mframe); in fill_registers()
377 y_virstride = hor_virstride * ver_virstride; in fill_registers()
378 uv_virstride = hor_virstride * ver_virstride / 2; in fill_registers()
380 is_fbc, y_virstride, hor_virstride, ver_virstride); in fill_registers()
388 fbd_offset = regs->avs2d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 64) * 4; in fill_registers()
H A Dhal_avs2d_rkv.c347 RK_U32 ver_virstride = 0; in fill_registers() local
351 ver_virstride = mpp_frame_get_ver_stride(mframe); in fill_registers()
352 y_virstride = hor_virstride * ver_virstride; in fill_registers()
353 …ride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride); in fill_registers()
357 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
H A Dhal_avs2d_vdpu382.c403 RK_U32 ver_virstride = 0; in fill_registers() local
407 ver_virstride = mpp_frame_get_ver_stride(mframe); in fill_registers()
408 y_virstride = hor_virstride * ver_virstride; in fill_registers()
409 …ride %d, hor_virstride %d, ver_virstride %d\n", is_fbc, y_virstride, hor_virstride, ver_virstride); in fill_registers()
413 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in fill_registers()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu384a.c365 RK_U32 ver_virstride = 0; in set_registers() local
371 ver_virstride = mpp_frame_get_ver_stride(mframe); in set_registers()
372 y_virstride = hor_virstride * ver_virstride; in set_registers()
373 uv_virstride = hor_virstride * ver_virstride / 2; in set_registers()
379 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
H A Dhal_h264d_rkv_reg.c452 RK_U32 ver_virstride = 0; in set_registers() local
458 ver_virstride = mpp_frame_get_ver_stride(mframe); in set_registers()
459 y_virstride = hor_virstride * ver_virstride; in set_registers()
H A Dhal_h264d_vdpu383.c429 RK_U32 ver_virstride = 0; in set_registers() local
435 ver_virstride = mpp_frame_get_ver_stride(mframe); in set_registers()
436 y_virstride = hor_virstride * ver_virstride; in set_registers()
437 uv_virstride = hor_virstride * ver_virstride / 2; in set_registers()
443 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in set_registers()
H A Dhal_h264d_vdpu34x.c549 RK_U32 ver_virstride = 0; in set_registers() local
554 ver_virstride = mpp_frame_get_ver_stride(mframe); in set_registers()
555 y_virstride = hor_virstride * ver_virstride; in set_registers()
559 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
H A Dhal_h264d_vdpu382.c558 RK_U32 ver_virstride = 0; in set_registers() local
563 ver_virstride = mpp_frame_get_ver_stride(mframe); in set_registers()
564 y_virstride = hor_virstride * ver_virstride; in set_registers()
568 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 16) / 16, SZ_4K); in set_registers()
/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu384a.c876 RK_U32 ver_virstride; in hal_h265d_vdpu384a_gen_regs() local
892 ver_virstride = mpp_frame_get_ver_stride(mframe); in hal_h265d_vdpu384a_gen_regs()
894 virstrid_y = ver_virstride * stride_y; in hal_h265d_vdpu384a_gen_regs()
898 virstrid_uv = stride_uv * ver_virstride; in hal_h265d_vdpu384a_gen_regs()
900 virstrid_uv = stride_uv * ver_virstride / 2; in hal_h265d_vdpu384a_gen_regs()
911 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in hal_h265d_vdpu384a_gen_regs()
H A Dhal_h265d_vdpu383.c964 RK_U32 ver_virstride; in hal_h265d_vdpu383_gen_regs() local
980 ver_virstride = mpp_frame_get_ver_stride(mframe); in hal_h265d_vdpu383_gen_regs()
982 virstrid_y = ver_virstride * stride_y; in hal_h265d_vdpu383_gen_regs()
986 virstrid_uv = stride_uv * ver_virstride; in hal_h265d_vdpu383_gen_regs()
988 virstrid_uv = stride_uv * ver_virstride / 2; in hal_h265d_vdpu383_gen_regs()
996 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16; in hal_h265d_vdpu383_gen_regs()
H A Dhal_h265d_vdpu382.c728 RK_U32 ver_virstride; in hal_h265d_vdpu382_gen_regs() local
733 ver_virstride = mpp_frame_get_ver_stride(mframe); in hal_h265d_vdpu382_gen_regs()
735 virstrid_y = ver_virstride * stride_y; in hal_h265d_vdpu382_gen_regs()
748 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu382_gen_regs()
H A Dhal_h265d_vdpu34x.c937 RK_U32 ver_virstride; in hal_h265d_vdpu34x_gen_regs() local
942 ver_virstride = mpp_frame_get_ver_stride(mframe); in hal_h265d_vdpu34x_gen_regs()
944 virstrid_y = ver_virstride * stride_y; in hal_h265d_vdpu34x_gen_regs()
959 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (ver_virstride + 64) / 16, SZ_4K); in hal_h265d_vdpu34x_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/av1d/
H A Dhal_av1d_vdpu383.c2327 RK_U32 ver_virstride = 0; in vdpu383_av1d_gen_regs() local
2335 ver_virstride = mpp_frame_get_ver_stride(mframe); in vdpu383_av1d_gen_regs()
2336 y_virstride = hor_virstride * ver_virstride; in vdpu383_av1d_gen_regs()
2337 uv_virstride = hor_virstride * ver_virstride / 2; in vdpu383_av1d_gen_regs()
2370 ver_virstride = mpp_frame_get_ver_stride(mframe); in vdpu383_av1d_gen_regs()
2371 y_virstride = hor_virstride * ver_virstride; in vdpu383_av1d_gen_regs()