| /rockchip-linux_mpp/mpp/hal/rkdec/h265d/ |
| H A D | hal_h265d_rkv.c | 358 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v345_output_pps_packet()
370 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v345_output_pps_packet()
371 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v345_output_pps_packet()
382 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
569 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_output_pps_packet()
596 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_output_pps_packet()
867 hw_regs->sw_interrupt.sw_wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_rkv_gen_regs()
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| H A D | hal_h265d_vdpu34x.c | 321 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v345_output_pps_packet()
333 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v345_output_pps_packet()
334 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v345_output_pps_packet()
345 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
546 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1); in hal_h265d_output_pps_packet()
572 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_output_pps_packet()
1027 hw_regs->common.reg012.wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_vdpu34x_gen_regs()
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| H A D | hal_h265d_vdpu382.c | 314 mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag , 1 ); in hal_h265d_v382_output_pps_packet()
326 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_columns_minus1 + 1 : 0, … in hal_h265d_v382_output_pps_packet()
327 …mpp_put_bits(&bp, dxva_cxt->pp.tiles_enabled_flag ? dxva_cxt->pp.num_tile_rows_minus1 + 1 : 0 , 5 … in hal_h265d_v382_output_pps_packet()
338 if (dxva_cxt->pp.tiles_enabled_flag) { in hal_h265d_v382_output_pps_packet()
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| H A D | hal_h265d_vdpu384a.c | 444 mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag, 1); in hal_h265d_v345_output_pps_packet()
514 …mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_columns_minus1 + 1) : 1… in hal_h265d_v345_output_pps_packet()
515 …mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_rows_minus1 + 1) : 1, 5… in hal_h265d_v345_output_pps_packet()
524 if (dxva_ctx->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
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| H A D | hal_h265d_vdpu383.c | 476 mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag, 1); in hal_h265d_v345_output_pps_packet()
546 …mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_columns_minus1 + 1) : 1… in hal_h265d_v345_output_pps_packet()
547 …mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_rows_minus1 + 1) : 1, 5… in hal_h265d_v345_output_pps_packet()
556 if (dxva_ctx->pp.tiles_enabled_flag) { in hal_h265d_v345_output_pps_packet()
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| /rockchip-linux_mpp/mpp/common/ |
| H A D | h265d_syntax.h | 137 UINT32 tiles_enabled_flag : 1; member
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| H A D | h265e_syntax_new.h | 95 RK_U32 tiles_enabled_flag : 1; member
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| /rockchip-linux_mpp/mpp/codec/dec/h265/ |
| H A D | h265d_ps.c | 941 if (openhevc_pps->tiles_enabled_flag != pps->tiles_enabled_flag) { in compare_pps()
2024 READ_ONEBIT(gb, &pps->tiles_enabled_flag); in mpp_hevc_decode_nal_pps()
2033 RK_S32 max_supt_height = pps->tiles_enabled_flag ? PIXH_1080P : PIXW_1080P; in mpp_hevc_decode_nal_pps()
2037 max_supt_height = pps->tiles_enabled_flag ? PIXH_8Kx4K : PIXW_8Kx4K; in mpp_hevc_decode_nal_pps()
2040 max_supt_height = pps->tiles_enabled_flag ? PIXH_4Kx2K : PIXW_4Kx2K; in mpp_hevc_decode_nal_pps()
2043 … if (sps->width > max_supt_width || (sps->height > max_supt_height && pps->tiles_enabled_flag) in mpp_hevc_decode_nal_pps()
2058 if (pps->tiles_enabled_flag) { in mpp_hevc_decode_nal_pps()
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| H A D | h265d_parser2_syntax.c | 132 … (pps->tiles_enabled_flag << 7) | in fill_picture_parameters()
148 if (pps->tiles_enabled_flag) { in fill_picture_parameters()
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| H A D | h265d_parser.h | 338 RK_U8 tiles_enabled_flag; member
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| H A D | h265d_parser.c | 1057 if (s->pps->tiles_enabled_flag || s->pps->entropy_coding_sync_enabled_flag) { in hls_slice_header()
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| /rockchip-linux_mpp/mpp/hal/rkenc/h265e/ |
| H A D | hal_h265e_vepu580.c | 270 if (!syn->pp.tiles_enabled_flag) { in vepu580_h265_set_me_ram()
2477 if (syn->pp.tiles_enabled_flag) { in vepu580_h265_set_hw_address()
2537 RK_S32 tiles_enabled_flag) in vepu580_h265e_save_pass1_patch() argument
2559 if (tiles_enabled_flag) in vepu580_h265e_save_pass1_patch()
2804 vepu580_setup_split(regs, cfg, syn->pp.tiles_enabled_flag); in hal_h265e_v580_gen_regs()
2813 if (syn->pp.tiles_enabled_flag) { in hal_h265e_v580_set_uniform_tile()
2847 regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v580_set_uniform_tile()
2942 vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag); in hal_h265e_v580_start()
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| H A D | hal_h265e_vepu541.c | 1331 if (syn->pp.tiles_enabled_flag == 0) { in vepu540_h265_set_me_ram()
1417 if (syn->pp.tiles_enabled_flag) { in vepu54x_h265_set_hw_address()
1640 if (syn->pp.tiles_enabled_flag) { in hal_h265e_v540_set_uniform_tile()
1647 regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag; in hal_h265e_v540_set_uniform_tile()
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| H A D | hal_h265e_vepu510.c | 1684 RK_S32 tiles_enabled_flag) in vepu510_h265e_save_pass1_patch() argument
1705 if (tiles_enabled_flag) in vepu510_h265e_save_pass1_patch()
2017 setup_vepu510_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag); in hal_h265e_v510_gen_regs()
2065 vepu510_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag); in hal_h265e_v510_gen_regs()
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| H A D | hal_h265e_vepu511.c | 661 RK_S32 tiles_enabled_flag) in vepu511_h265e_save_pass1_patch() argument
682 if (tiles_enabled_flag) in vepu511_h265e_save_pass1_patch()
2227 vepu511_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag); in hal_h265e_vepu511_gen_regs()
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| H A D | hal_h265e_vepu540c.c | 1310 vepu540c_h265_set_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag); in hal_h265e_v540c_gen_regs()
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