Searched refs:sw_dec_mode (Results 1 – 17 of 17) sorted by relevance
185 p_regs->sw53.sw_dec_mode = 8; in hal_m2vd_vdpu2_init_hwcfg()216 p_regs->sw53.sw_dec_mode = 5; in hal_m2vd_vdpu2_gen_regs()223 p_regs->sw53.sw_dec_mode = 6; in hal_m2vd_vdpu2_gen_regs()
58 RK_U32 sw_dec_mode; member
104 RK_U32 sw_dec_mode : 2 ; member
87 RK_U32 sw_dec_mode : 4; member
66 regs->SwReg03.sw_dec_mode = 2; in vpu1_h263d_setup_regs_by_syntax()
88 RK_U32 sw_dec_mode : 4; member
94 regs->SwReg03.sw_dec_mode = 1; in vdpu1_mpg4d_setup_regs_by_syntax()
74 RK_U32 sw_dec_mode : 2; member
298 vp9_hw_regs->swreg2_sysctrl.sw_dec_mode = 2; //set as vp9 dec in hal_vp9d_rkv_gen_regs()
89 RK_U32 sw_dec_mode : 4; member
691 p_reg->SwReg03.sw_dec_mode = 0; /* set H264 mode */ in vdpu1_set_device_regs()
102 RK_U32 sw_dec_mode : 4; member
189 reg->reg3.sw_dec_mode = DEC_MODE_VP8; in hal_vp8_init_hwcfg()
307 RK_U32 sw_dec_mode : 4; member
654 reg->reg3.sw_dec_mode = 3; in jpegd_gen_regs()
1595 RK_U32 sw_dec_mode : 5; member
1936 regs->swreg3.sw_dec_mode = 17; // av1 mode in vdpu_av1d_gen_regs()