Searched refs:reg3 (Results 1 – 11 of 11) sorted by relevance
575 regs->reg3.sw_dec_out_dis = 1; in jpegd_setup_pp()591 regs->reg3.sw_dec_out_dis = 0; in jpegd_setup_pp()628 reg->reg3.sw_dec_axi_wr_id = 0; in jpegd_regs_init()651 reg->reg3.sw_filtering_dis = 1; in jpegd_gen_regs()654 reg->reg3.sw_dec_mode = 3; in jpegd_gen_regs()655 reg->reg3.sw_pjpeg_e = 0; /* Set JPEG operation mode */ in jpegd_gen_regs()656 reg->reg3.sw_dec_out_dis = 0; in jpegd_gen_regs()657 reg->reg3.sw_rlc_mode_e = 0; in jpegd_gen_regs()
308 } reg3; member
56 } reg3; member
374 reg->reg3.sw_pp_color_coefff = BRIGHTNESS; /* brightness */ in jpegd_setup_pp()
187 reg->reg3.sw_dec_out_dis = 0; in hal_vp8_init_hwcfg()188 reg->reg3.sw_dec_axi_wr_id = 0; in hal_vp8_init_hwcfg()189 reg->reg3.sw_dec_mode = DEC_MODE_VP8; in hal_vp8_init_hwcfg()524 regs->reg3.sw_pic_inter_e = pic_param->frame_type; in hal_vp8d_vdpu1_gen_regs()525 regs->reg3.sw_skip_mode = !pic_param->mb_no_coeff_skip; in hal_vp8d_vdpu1_gen_regs()557 regs->reg3.sw_filtering_dis = 1; in hal_vp8d_vdpu1_gen_regs()
103 } reg3; member
407 dst_reg->dci.reg3.sw_dci_data_format = src_params->dci_format; in set_hist_to_vdpp2_reg()408 dst_reg->dci.reg3.sw_dci_csc_range = src_params->dci_csc_range; in set_hist_to_vdpp2_reg()409 dst_reg->dci.reg3.sw_dci_vsd_mode = dci_vsd_mode; in set_hist_to_vdpp2_reg()410 dst_reg->dci.reg3.sw_dci_hsd_mode = dci_hsd_mode; in set_hist_to_vdpp2_reg()411 dst_reg->dci.reg3.sw_dci_alpha_swap = src_params->dci_alpha_swap; in set_hist_to_vdpp2_reg()412 dst_reg->dci.reg3.sw_dci_rb_swap = src_params->dci_rbuv_swap; in set_hist_to_vdpp2_reg()413 dst_reg->dci.reg3.sw_dci_blk_hsize = sw_dci_blk_hsize; in set_hist_to_vdpp2_reg()414 dst_reg->dci.reg3.sw_dci_blk_vsize = sw_dci_blk_vsize; in set_hist_to_vdpp2_reg()447 dst_reg->es.reg3.ep_chk_en = p_es_param->es_bEndpointCheckEnable; in set_es_to_vdpp2_reg()817 dst_reg->sharp.reg3.sw_peaking_v20 = p_shp_param->peaking_filt_core_V2[0]; in set_shp_to_vdpp2_reg()[all …]
681 dmsr->reg3.sw_dmsr_edge_low_thre_3 = p_dmsr_param->dmsr_edge_th_low_arr[3]; in set_dmsr_to_vdpp_reg()682 dmsr->reg3.sw_dmsr_edge_high_thre_3 = p_dmsr_param->dmsr_edge_th_high_arr[3]; in set_dmsr_to_vdpp_reg()843 zme->common.reg3.vir_width = zme_params->src_width; in set_zme_to_vdpp_reg()844 zme->common.reg3.vir_height = zme_params->src_height; in set_zme_to_vdpp_reg()
47 RK_U32 reg3; // 0x000C member
83 } reg3; /* 0x008C */ member278 } reg3; /* 0x000c */ member622 } reg3; /* 0x020c */ member966 } reg3; /* 0x040c */ member1310 } reg3; /* 0x060c */ member1651 } reg3; /* 0x080C */ member
57 } reg3; // 0x000C member226 } reg3; // 0x00EC member256 } reg3; // 0x010C member429 } reg3; // 0x020C member