407     dst_reg->dci.reg3.sw_dci_data_format = src_params->dci_format;  in set_hist_to_vdpp2_reg()
408     dst_reg->dci.reg3.sw_dci_csc_range = src_params->dci_csc_range;  in set_hist_to_vdpp2_reg()
409     dst_reg->dci.reg3.sw_dci_vsd_mode = dci_vsd_mode;  in set_hist_to_vdpp2_reg()
410     dst_reg->dci.reg3.sw_dci_hsd_mode = dci_hsd_mode;  in set_hist_to_vdpp2_reg()
411     dst_reg->dci.reg3.sw_dci_alpha_swap = src_params->dci_alpha_swap;  in set_hist_to_vdpp2_reg()
412     dst_reg->dci.reg3.sw_dci_rb_swap = src_params->dci_rbuv_swap;  in set_hist_to_vdpp2_reg()
413     dst_reg->dci.reg3.sw_dci_blk_hsize = sw_dci_blk_hsize;  in set_hist_to_vdpp2_reg()
414     dst_reg->dci.reg3.sw_dci_blk_vsize = sw_dci_blk_vsize;  in set_hist_to_vdpp2_reg()
447     dst_reg->es.reg3.ep_chk_en = p_es_param->es_bEndpointCheckEnable;  in set_es_to_vdpp2_reg()
817     dst_reg->sharp.reg3.sw_peaking_v20  = p_shp_param->peaking_filt_core_V2[0];  in set_shp_to_vdpp2_reg()
818     dst_reg->sharp.reg3.sw_peaking_v21  = p_shp_param->peaking_filt_core_V2[1];  in set_shp_to_vdpp2_reg()
819     dst_reg->sharp.reg3.sw_peaking_v22  = p_shp_param->peaking_filt_core_V2[2];  in set_shp_to_vdpp2_reg()
820     dst_reg->sharp.reg3.sw_peaking_usm0 = p_shp_param->peaking_filt_core_USM[0];  in set_shp_to_vdpp2_reg()
821     dst_reg->sharp.reg3.sw_peaking_usm1 = p_shp_param->peaking_filt_core_USM[1];  in set_shp_to_vdpp2_reg()
822     dst_reg->sharp.reg3.sw_peaking_usm2 = p_shp_param->peaking_filt_core_USM[2];  in set_shp_to_vdpp2_reg()
823     dst_reg->sharp.reg3.sw_diag_coef    = p_shp_param->peaking_filter_cfg_diag_enh_coef;  in set_shp_to_vdpp2_reg()