Searched refs:reg012 (Results 1 – 14 of 14) sorted by relevance
274 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN; in init_common_regs()275 common->reg012.info_collect_en = 1; in init_common_regs()276 common->reg012.error_info_en = 0; in init_common_regs()343 if (hw_regs->common.reg012.fbc_e) in avs2d_refine_rcb_size()415 common->reg012.fbc_e = 1; in fill_registers()420 common->reg012.fbc_e = 0; in fill_registers()534 p_regs->common.reg012.scale_down_en = 0; in fill_registers()726 regs->common.reg012.scanlist_addr_valid_en = 1; in hal_avs2d_vdpu382_gen_regs()
273 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN; in init_common_regs()274 common->reg012.wr_ddr_align_en = 1; in init_common_regs()275 common->reg012.info_collect_en = 1; in init_common_regs()276 common->reg012.error_info_en = 0; in init_common_regs()359 common->reg012.fbc_e = 1; in fill_registers()364 common->reg012.fbc_e = 0; in fill_registers()659 regs->common.reg012.scanlist_addr_valid_en = 1; in hal_avs2d_rkv_gen_regs()
542 common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; in set_registers()561 common->reg012.fbc_e = 1; in set_registers()566 common->reg012.fbc_e = 0; in set_registers()679 common->reg012.wait_reset_en = 1; in init_common_regs()837 if (regs->common.reg012.fbc_e) { in h264d_refine_rcb_size()984 regs->common.reg012.scanlist_addr_valid_en = 1; in vdpu34x_h264d_gen_regs()
549 common->reg012.colmv_compress_en = in set_registers()551 common->reg012.info_collect_en = 1; in set_registers()570 common->reg012.fbc_e = 1; in set_registers()575 common->reg012.fbc_e = 0; in set_registers()874 if (regs->common.reg012.fbc_e) { in h264d_refine_rcb_size()1012 regs->common.reg012.scanlist_addr_valid_en = 1; in vdpu382_h264d_gen_regs()1039 regs->common.reg012.scale_down_en = 0; in vdpu382_h264d_gen_regs()
420 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v382_output_pps_packet()514 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()523 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()750 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu382_gen_regs()755 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu382_gen_regs()810 hw_regs->common.reg012.colmv_compress_en = reg_ctx->hw_info ? in hal_h265d_vdpu382_gen_regs()937 hw_regs->common.reg012.scale_down_en = 0; in hal_h265d_vdpu382_gen_regs()
427 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v345_output_pps_packet()742 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()751 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()961 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu34x_gen_regs()966 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu34x_gen_regs()995 hw_regs->common.reg012.wait_reset_en = 1; in hal_h265d_vdpu34x_gen_regs()1027 hw_regs->common.reg012.wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_vdpu34x_gen_regs()1029 hw_regs->common.reg012.colmv_compress_en = COLMV_COMPRESS_EN; in hal_h265d_vdpu34x_gen_regs()
317 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()323 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()609 …vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress… in hal_vp9d_vdpu34x_gen_regs()635 vp9_hw_regs->common.reg012.fbc_e = 1; in hal_vp9d_vdpu34x_gen_regs()644 vp9_hw_regs->common.reg012.fbc_e = 0; in hal_vp9d_vdpu34x_gen_regs()798 vp9_hw_regs->common.reg012.wait_reset_en = 1; in hal_vp9d_vdpu34x_gen_regs()
326 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()334 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()619 …vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress… in hal_vp9d_vdpu382_gen_regs()645 vp9_hw_regs->common.reg012.fbc_e = 1; in hal_vp9d_vdpu382_gen_regs()654 vp9_hw_regs->common.reg012.fbc_e = 0; in hal_vp9d_vdpu382_gen_regs()873 vp9_hw_regs->common.reg012.scale_down_en = 0; in hal_vp9d_vdpu382_gen_regs()
167 RK_U32 reg012; member
241 com->reg012.scale_down_en = 1; in vdpu382_setup_down_scale()
466 regs->reg012.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu541_prep()467 regs->reg012.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu541_prep()468 regs->reg012.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu541_prep()469 regs->reg012.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu541_prep()1309 RK_U32 pic_temp = ((regs->reg012.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in setup_vepu541_me()
257 } reg012; member
117 } reg012; member
122 } reg012; member