Searched refs:rc_dthd_0_8 (Results 1 – 14 of 14) sorted by relevance
970 regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu540c_rc_base()971 regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu540c_rc_base()972 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu540c_rc_base()973 regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu540c_rc_base()974 regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu540c_rc_base()975 regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu540c_rc_base()976 regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu540c_rc_base()977 regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu540c_rc_base()978 regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu540c_rc_base()
1324 regs->reg_rc_klut.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu580_rc_base()1325 regs->reg_rc_klut.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu580_rc_base()1326 regs->reg_rc_klut.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu580_rc_base()1327 regs->reg_rc_klut.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu580_rc_base()1328 regs->reg_rc_klut.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu580_rc_base()1329 regs->reg_rc_klut.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu580_rc_base()1330 regs->reg_rc_klut.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu580_rc_base()1331 regs->reg_rc_klut.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu580_rc_base()1332 regs->reg_rc_klut.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu580_rc_base()
1263 regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu510_rc_base()1264 regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu510_rc_base()1265 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu510_rc_base()1266 regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu510_rc_base()1267 regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu510_rc_base()1268 regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu510_rc_base()1269 regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu510_rc_base()1270 regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu510_rc_base()1271 regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu510_rc_base()
1255 regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd; in setup_vepu511_rc_base()1256 regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd; in setup_vepu511_rc_base()1257 regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd; in setup_vepu511_rc_base()1258 regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd; in setup_vepu511_rc_base()1259 regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF; in setup_vepu511_rc_base()1260 regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF; in setup_vepu511_rc_base()1261 regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF; in setup_vepu511_rc_base()1262 regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF; in setup_vepu511_rc_base()1263 regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF; in setup_vepu511_rc_base()
726 RK_U32 rc_dthd_0_8[9]; member
732 RK_U32 rc_dthd_0_8[9]; member
749 reg_rc->rc_dthd_0_8[0] = 4 * negative_bits_thd; in vepu540c_h265_set_rc_regs()750 reg_rc->rc_dthd_0_8[1] = negative_bits_thd; in vepu540c_h265_set_rc_regs()751 reg_rc->rc_dthd_0_8[2] = positive_bits_thd; in vepu540c_h265_set_rc_regs()752 reg_rc->rc_dthd_0_8[3] = 4 * positive_bits_thd; in vepu540c_h265_set_rc_regs()753 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF; in vepu540c_h265_set_rc_regs()754 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF; in vepu540c_h265_set_rc_regs()755 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF; in vepu540c_h265_set_rc_regs()756 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF; in vepu540c_h265_set_rc_regs()757 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF; in vepu540c_h265_set_rc_regs()
1363 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd; in vepu510_h265_set_rc_regs()1364 reg_rc->rc_dthd_0_8[1] = negative_bits_thd; in vepu510_h265_set_rc_regs()1365 reg_rc->rc_dthd_0_8[2] = positive_bits_thd; in vepu510_h265_set_rc_regs()1366 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd; in vepu510_h265_set_rc_regs()1367 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF; in vepu510_h265_set_rc_regs()1368 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF; in vepu510_h265_set_rc_regs()1369 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF; in vepu510_h265_set_rc_regs()1370 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF; in vepu510_h265_set_rc_regs()1371 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF; in vepu510_h265_set_rc_regs()
1324 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd; in vepu511_h265_set_rc_regs()1325 reg_rc->rc_dthd_0_8[1] = negative_bits_thd; in vepu511_h265_set_rc_regs()1326 reg_rc->rc_dthd_0_8[2] = positive_bits_thd; in vepu511_h265_set_rc_regs()1327 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd; in vepu511_h265_set_rc_regs()1328 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF; in vepu511_h265_set_rc_regs()1329 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF; in vepu511_h265_set_rc_regs()1330 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF; in vepu511_h265_set_rc_regs()1331 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF; in vepu511_h265_set_rc_regs()1332 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF; in vepu511_h265_set_rc_regs()
1934 reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd; in vepu580_h265_set_rc_regs()1935 reg_rc->rc_dthd_0_8[1] = negative_bits_thd; in vepu580_h265_set_rc_regs()1936 reg_rc->rc_dthd_0_8[2] = positive_bits_thd; in vepu580_h265_set_rc_regs()1937 reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd; in vepu580_h265_set_rc_regs()1938 reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF; in vepu580_h265_set_rc_regs()1939 reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF; in vepu580_h265_set_rc_regs()1940 reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF; in vepu580_h265_set_rc_regs()1941 reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF; in vepu580_h265_set_rc_regs()1942 reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF; in vepu580_h265_set_rc_regs()
874 RK_U32 rc_dthd_0_8[9]; member
751 RK_U32 rc_dthd_0_8[9]; member
747 RK_U32 rc_dthd_0_8[9]; member
1158 RK_U32 rc_dthd_0_8[9]; member