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Searched refs:r_coeff (Results 1 – 11 of 11) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.c29 ._2y = {.r_coeff = 66, .g_coeff = 129, .b_coeff = 25, .offset = 16},
30 ._2u = {.r_coeff = -38, .g_coeff = -74, .b_coeff = 112, .offset = 128},
31 ._2v = {.r_coeff = 112, .g_coeff = -94, .b_coeff = -18, .offset = 128},
36 ._2y = {.r_coeff = 47, .g_coeff = 157, .b_coeff = 16, .offset = 16},
37 ._2u = {.r_coeff = -26, .g_coeff = -87, .b_coeff = 112, .offset = 128},
38 ._2v = {.r_coeff = 112, .g_coeff = -102, .b_coeff = -10, .offset = 128},
46 ._2y = {.r_coeff = 77, .g_coeff = 150, .b_coeff = 29, .offset = 0},
47 ._2u = {.r_coeff = -43, .g_coeff = -85, .b_coeff = 128, .offset = 128},
48 ._2v = {.r_coeff = 128, .g_coeff = -107, .b_coeff = -21, .offset = 128},
53 ._2y = {.r_coeff = 54, .g_coeff = 183, .b_coeff = 18, .offset = 0},
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H A Dvepu5xx_common.h79 RK_S16 r_coeff; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c502 regs->reg018.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu541_prep()
506 regs->reg019.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu541_prep()
510 regs->reg020.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu541_prep()
H A Dhal_h264e_vepu540c.c494 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu540c_prep()
498 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu540c_prep()
502 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu540c_prep()
H A Dhal_h264e_vepu580.c775 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu580_prep()
779 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
783 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu580_prep()
H A Dhal_h264e_vepu510.c791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu510_prep()
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu510_prep()
799 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu510_prep()
H A Dhal_h264e_vepu511.c768 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu511_prep()
772 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu511_prep()
776 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu511_prep()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c829 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu540c_h265_set_pp_regs()
833 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu540c_h265_set_pp_regs()
837 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu540c_h265_set_pp_regs()
H A Dhal_h265e_vepu541.c1107 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff; in vepu541_h265_set_pp_regs()
1111 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff; in vepu541_h265_set_pp_regs()
1115 regs->src_udfv.wght_r2v = cfg_coeffs->_2v.r_coeff; in vepu541_h265_set_pp_regs()
H A Dhal_h265e_vepu510.c1475 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu510_h265_set_pp_regs()
1479 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu510_h265_set_pp_regs()
1483 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu510_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c2039 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu580_h265_set_pp_regs()
2043 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu580_h265_set_pp_regs()
2047 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu580_h265_set_pp_regs()