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Searched refs:mpp_dev_set_reg_offset (Results 1 – 25 of 56) sorted by relevance

123

/rockchip-linux_mpp/mpp/hal/rkdec/
H A Dvdpu382_com.c91 mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset); in vdpu382_setup_rcb()
93 mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset); in vdpu382_setup_rcb()
95 mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset); in vdpu382_setup_rcb()
97 mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset); in vdpu382_setup_rcb()
99 mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset); in vdpu382_setup_rcb()
101 mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset); in vdpu382_setup_rcb()
103 mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset); in vdpu382_setup_rcb()
105 mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset); in vdpu382_setup_rcb()
107 mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset); in vdpu382_setup_rcb()
109 mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset); in vdpu382_setup_rcb()
[all …]
H A Dvdpu34x_com.c91 mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset); in vdpu34x_setup_rcb()
93 mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset); in vdpu34x_setup_rcb()
95 mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset); in vdpu34x_setup_rcb()
97 mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset); in vdpu34x_setup_rcb()
99 mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset); in vdpu34x_setup_rcb()
101 mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset); in vdpu34x_setup_rcb()
103 mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset); in vdpu34x_setup_rcb()
105 mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset); in vdpu34x_setup_rcb()
107 mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset); in vdpu34x_setup_rcb()
109 mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset); in vdpu34x_setup_rcb()
H A Dvdpu383_com.c95 mpp_dev_set_reg_offset(dev, info[i].reg_idx, info[i].offset); in vdpu383_setup_rcb()
294 mpp_dev_set_reg_offset(dev, 133, down_scale_y_offset); in vdpu383_setup_down_scale()
H A Dvdpu384a_com.c107 mpp_dev_set_reg_offset(dev, info[i].reg_idx, info[i].offset); in vdpu384a_setup_rcb()
306 mpp_dev_set_reg_offset(dev, 133, down_scale_y_offset); in vdpu384a_setup_down_scale()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu540c_common.c147 mpp_dev_set_reg_offset(dev, 265, u_offset); in vepu540c_jpeg_set_patch_info()
151 mpp_dev_set_reg_offset(dev, 266, v_offset); in vepu540c_jpeg_set_patch_info()
181 mpp_dev_set_reg_offset(cfg->dev, 258, mpp_packet_get_length(task->packet)); in vepu540c_set_jpeg_reg()
182 mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output)); in vepu540c_set_jpeg_reg()
H A Dvepu580_common.c80 mpp_dev_set_reg_offset(dev, VEPU580_OSD_ADDR_IDX_BASE + k, tmp->buf_offset); in vepu580_set_osd()
H A Dvepu541_common.c314 mpp_dev_set_reg_offset(dev, VEPU541_OSD_ADDR_IDX_BASE + i, tmp->buf_offset); in vepu541_set_osd()
515 mpp_dev_set_reg_offset(dev, VEPU541_OSD_ADDR_IDX_BASE + k, tmp->buf_offset); in vepu540_set_osd()
/rockchip-linux_mpp/mpp/hal/vpu/vp8d/
H A Dhal_vp8d_vdpu2.c270 mpp_dev_set_reg_offset(ctx->dev, 145, pic_param->stream_start_offset); in hal_vp8d_dct_partition_cfg()
299 mpp_dev_set_reg_offset(ctx->dev, 64, addr); in hal_vp8d_dct_partition_cfg()
303 mpp_dev_set_reg_offset(ctx->dev, 139 + i, addr); in hal_vp8d_dct_partition_cfg()
307 mpp_dev_set_reg_offset(ctx->dev, 140 + i, addr); in hal_vp8d_dct_partition_cfg()
480 mpp_dev_set_reg_offset(ctx->dev, 131, mb_width * mb_height); in hal_vp8d_vdpu2_gen_regs()
498 mpp_dev_set_reg_offset(ctx->dev, 136, pic_param->ref_frame_sign_bias_golden); in hal_vp8d_vdpu2_gen_regs()
511 mpp_dev_set_reg_offset(ctx->dev, 137, pic_param->ref_frame_sign_bias_altref); in hal_vp8d_vdpu2_gen_regs()
515 mpp_dev_set_reg_offset(ctx->dev, 149, pic_param->stVP8Segments.segmentation_enabled in hal_vp8d_vdpu2_gen_regs()
H A Dhal_vp8d_vdpu1.c273 mpp_dev_set_reg_offset(ctx->dev, 27, pic_param->stream_start_offset); in hal_vp8d_dct_partition_cfg()
302 mpp_dev_set_reg_offset(ctx->dev, 12, addr); in hal_vp8d_dct_partition_cfg()
307 mpp_dev_set_reg_offset(ctx->dev, 21 + i, addr); in hal_vp8d_dct_partition_cfg()
312 mpp_dev_set_reg_offset(ctx->dev, 22 + i, addr); in hal_vp8d_dct_partition_cfg()
487 mpp_dev_set_reg_offset(ctx->dev, 14, (mb_width * mb_height) << 8); in hal_vp8d_vdpu1_gen_regs()
504 mpp_dev_set_reg_offset(ctx->dev, 18, pic_param->ref_frame_sign_bias_golden); in hal_vp8d_vdpu1_gen_regs()
516 mpp_dev_set_reg_offset(ctx->dev, 19, pic_param->ref_frame_sign_bias_altref); in hal_vp8d_vdpu1_gen_regs()
520 mpp_dev_set_reg_offset(ctx->dev, 10, (pic_param->stVP8Segments.segmentation_enabled in hal_vp8d_vdpu1_gen_regs()
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu1_v2.c146 mpp_dev_set_reg_offset(dev, 11, offset); in hal_jpege_vepu1_set_extra_info()
153 mpp_dev_set_reg_offset(dev, 12, offset); in hal_jpege_vepu1_set_extra_info()
158 mpp_dev_set_reg_offset(dev, 13, offset); in hal_jpege_vepu1_set_extra_info()
164 mpp_dev_set_reg_offset(dev, 11, offset); in hal_jpege_vepu1_set_extra_info()
277 mpp_dev_set_reg_offset(ctx->dev, 5, bytepos); in hal_jpege_vepu1_gen_regs()
510 mpp_dev_set_reg_offset(ctx->dev, 5, ctx->part_bytepos); in hal_jpege_vepu1_part_start()
H A Dhal_jpege_vepu2_v2.c355 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_Y, cfg.offset_byte[0]); in hal_jpege_vepu2_set_extra_info()
358 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_U, cfg.offset_byte[1]); in hal_jpege_vepu2_set_extra_info()
361 mpp_dev_set_reg_offset(dev, VEPU2_REG_INPUT_V, cfg.offset_byte[2]); in hal_jpege_vepu2_set_extra_info()
468 mpp_dev_set_reg_offset(ctx->dev, 77, bytepos); in hal_jpege_vepu2_gen_regs()
944 mpp_dev_set_reg_offset(ctx->dev, 77, ctx->part_bytepos); in hal_jpege_vepu2_part_start()
/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c441 mpp_dev_set_reg_offset(p_hal->dev, 101, offset); in set_ref_cb_base()
444 mpp_dev_set_reg_offset(p_hal->dev, 103, offset); in set_ref_cb_base()
447 mpp_dev_set_reg_offset(p_hal->dev, 105, offset); in set_ref_cb_base()
450 mpp_dev_set_reg_offset(p_hal->dev, 107, offset); in set_ref_cb_base()
453 mpp_dev_set_reg_offset(p_hal->dev, 109, offset); in set_ref_cb_base()
456 mpp_dev_set_reg_offset(p_hal->dev, 111, offset); in set_ref_cb_base()
459 mpp_dev_set_reg_offset(p_hal->dev, 113, offset); in set_ref_cb_base()
503 mpp_dev_set_reg_offset(p_hal->dev, 135, offset); in set_ref_dbase()
506 mpp_dev_set_reg_offset(p_hal->dev, 137, offset); in set_ref_dbase()
509 mpp_dev_set_reg_offset(p_hal->dev, 139, offset); in set_ref_dbase()
[all …]
/rockchip-linux_mpp/mpp/hal/vpu/vp8e/
H A Dhal_vp8e_vepu1_v2.c58 mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
71 mpp_dev_set_reg_offset(ctx->dev, 11, hw_cfg->input_lum_offset); in vp8e_vpu_frame_start()
75 mpp_dev_set_reg_offset(ctx->dev, 12, hw_cfg->input_cb_offset); in vp8e_vpu_frame_start()
79 mpp_dev_set_reg_offset(ctx->dev, 13, hw_cfg->input_cr_offset); in vp8e_vpu_frame_start()
198 mpp_dev_set_reg_offset(ctx->dev, 58, hw_cfg->partition_offset[0]); in vp8e_vpu_frame_start()
200 mpp_dev_set_reg_offset(ctx->dev, 59, hw_cfg->partition_offset[1]); in vp8e_vpu_frame_start()
H A Dhal_vp8e_vepu2_v2.c61 mpp_dev_set_reg_offset(ctx->dev, 77, hw_cfg->output_strm_offset); in vp8e_vpu_frame_start()
73 mpp_dev_set_reg_offset(ctx->dev, 48, hw_cfg->input_lum_offset); in vp8e_vpu_frame_start()
77 mpp_dev_set_reg_offset(ctx->dev, 49, hw_cfg->input_cb_offset); in vp8e_vpu_frame_start()
81 mpp_dev_set_reg_offset(ctx->dev, 50, hw_cfg->input_cr_offset); in vp8e_vpu_frame_start()
201 mpp_dev_set_reg_offset(ctx->dev, 44, hw_cfg->partition_offset[0]); in vp8e_vpu_frame_start()
203 mpp_dev_set_reg_offset(ctx->dev, 45, hw_cfg->partition_offset[1]); in vp8e_vpu_frame_start()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu1_v2.c268 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8); in setup_output_packet()
540 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2, in hal_h264e_vepu1_gen_regs_v2()
544 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2, in hal_h264e_vepu1_gen_regs_v2()
548 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2, in hal_h264e_vepu1_gen_regs_v2()
558 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REC_CHROMA >> 2, hw_bufs->yuv_size); in hal_h264e_vepu1_gen_regs_v2()
561 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REF_CHROMA >> 2, hw_bufs->yuv_size); in hal_h264e_vepu1_gen_regs_v2()
H A Dhal_h264e_vepu2_v2.c269 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8); in setup_output_packet()
607 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2, in hal_h264e_vepu2_gen_regs_v2()
611 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2, in hal_h264e_vepu2_gen_regs_v2()
615 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2, in hal_h264e_vepu2_gen_regs_v2()
625 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REC_CHROMA >> 2, hw_bufs->yuv_size); in hal_h264e_vepu2_gen_regs_v2()
628 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REF_CHROMA >> 2, hw_bufs->yuv_size); in hal_h264e_vepu2_gen_regs_v2()
/rockchip-linux_mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu1.c129 mpp_dev_set_reg_offset(p_hal->dev, 12, p_hal->data_offset); in set_regs_parameters()
137 mpp_dev_set_reg_offset(p_hal->dev, 13, p_syn->pp.horizontalSize); in set_regs_parameters()
384 mpp_dev_set_reg_offset(p_hal->dev, 41, offset); in set_regs_parameters()
399 mpp_dev_set_reg_offset(p_hal->dev, 16, 2); in set_regs_parameters()
400 mpp_dev_set_reg_offset(p_hal->dev, 17, 3); in set_regs_parameters()
H A Dhal_avsd_vdpu2.c121 mpp_dev_set_reg_offset(p_hal->dev, 64, p_hal->data_offset); in set_regs_parameters()
129 mpp_dev_set_reg_offset(p_hal->dev, 63, p_syn->pp.horizontalSize); in set_regs_parameters()
377 mpp_dev_set_reg_offset(p_hal->dev, 62, offset); in set_regs_parameters()
392 mpp_dev_set_reg_offset(p_hal->dev, 134, 2); in set_regs_parameters()
393 mpp_dev_set_reg_offset(p_hal->dev, 135, 3); in set_regs_parameters()
H A Dhal_avsd_plus.c136 mpp_dev_set_reg_offset(p_hal->dev, 12, p_hal->data_offset); in set_regs_parameters()
179 mpp_dev_set_reg_offset(p_hal->dev, 13, stride); in set_regs_parameters()
471 mpp_dev_set_reg_offset(p_hal->dev, 41, offset); in set_regs_parameters()
492 mpp_dev_set_reg_offset(p_hal->dev, 16, 2); in set_regs_parameters()
493 mpp_dev_set_reg_offset(p_hal->dev, 17, 3); in set_regs_parameters()
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vpu720.c513 mpp_dev_set_reg_offset(ctx->dev, 20, mpp_packet_get_length(task->packet)); in hal_jpege_vpu720_gen_regs()
514 mpp_dev_set_reg_offset(ctx->dev, 17, mpp_buffer_get_size(task->output)); in hal_jpege_vpu720_gen_regs()
515 mpp_dev_set_reg_offset(ctx->dev, 23, ctx->fmt_cfg.u_offset); in hal_jpege_vpu720_gen_regs()
516 mpp_dev_set_reg_offset(ctx->dev, 24, ctx->fmt_cfg.v_offset); in hal_jpege_vpu720_gen_regs()
H A Dhal_jpege_vepu511.c184 mpp_dev_set_reg_offset(dev, 265, u_offset); in vepu511_jpeg_set_patch_info()
188 mpp_dev_set_reg_offset(dev, 266, v_offset); in vepu511_jpeg_set_patch_info()
217 mpp_dev_set_reg_offset(cfg->dev, 258, mpp_packet_get_length(task->packet)); in vepu511_set_jpeg_reg()
218 mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output)); in vepu511_set_jpeg_reg()
/rockchip-linux_mpp/osal/inc/
H A Dmpp_device.h163 MPP_RET mpp_dev_set_reg_offset(MppDev dev, RK_S32 index, RK_U32 offset);
/rockchip-linux_mpp/mpp/hal/vpu/m2vd/
H A Dhal_m2vd_vdpu1.c218 mpp_dev_set_reg_offset(ctx->dev, 12, dx->bitstream_offset); in hal_m2vd_vdpu1_gen_regs()
228 mpp_dev_set_reg_offset(ctx->dev, 13, MPP_ALIGN(dx->seq.decode_width, 16)); in hal_m2vd_vdpu1_gen_regs()
H A Dhal_m2vd_vdpu2.c268 mpp_dev_set_reg_offset(ctx->dev, 64, dx->bitstream_offset); in hal_m2vd_vdpu2_gen_regs()
279 mpp_dev_set_reg_offset(ctx->dev, 63, MPP_ALIGN(dx->seq.decode_width, 16)); in hal_m2vd_vdpu2_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c772 mpp_dev_set_reg_offset(dev, 71, u_offset); in vepu541_h265_set_patch_info()
779 mpp_dev_set_reg_offset(dev, 72, v_offset); in vepu541_h265_set_patch_info()
784 mpp_dev_set_reg_offset(dev, 83, mpp_buffer_get_size(task->output)); in vepu541_h265_set_patch_info()
1405 mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len); in vepu54x_h265_set_hw_address()
1415 mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len); in vepu54x_h265_set_hw_address()
1449 mpp_dev_set_reg_offset(ctx->dev, 86, mpp_packet_get_length(task->packet)); in vepu54x_h265_set_hw_address()
1701 mpp_dev_set_reg_offset(ctx->dev, 86, offset); in hal_h265e_v540_start()
1702 mpp_dev_set_reg_offset(ctx->dev, 75, ctx->fbc_header_len); in hal_h265e_v540_start()
1703 mpp_dev_set_reg_offset(ctx->dev, 77, ctx->fbc_header_len); in hal_h265e_v540_start()

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