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Searched refs:g_coeff (Results 1 – 11 of 11) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.c29 ._2y = {.r_coeff = 66, .g_coeff = 129, .b_coeff = 25, .offset = 16},
30 ._2u = {.r_coeff = -38, .g_coeff = -74, .b_coeff = 112, .offset = 128},
31 ._2v = {.r_coeff = 112, .g_coeff = -94, .b_coeff = -18, .offset = 128},
36 ._2y = {.r_coeff = 47, .g_coeff = 157, .b_coeff = 16, .offset = 16},
37 ._2u = {.r_coeff = -26, .g_coeff = -87, .b_coeff = 112, .offset = 128},
38 ._2v = {.r_coeff = 112, .g_coeff = -102, .b_coeff = -10, .offset = 128},
46 ._2y = {.r_coeff = 77, .g_coeff = 150, .b_coeff = 29, .offset = 0},
47 ._2u = {.r_coeff = -43, .g_coeff = -85, .b_coeff = 128, .offset = 128},
48 ._2v = {.r_coeff = 128, .g_coeff = -107, .b_coeff = -21, .offset = 128},
53 ._2y = {.r_coeff = 54, .g_coeff = 183, .b_coeff = 18, .offset = 0},
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H A Dvepu5xx_common.h80 RK_S16 g_coeff; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c501 regs->reg018.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu541_prep()
505 regs->reg019.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu541_prep()
509 regs->reg020.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu541_prep()
H A Dhal_h264e_vepu540c.c493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
497 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu540c_prep()
501 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu540c_prep()
H A Dhal_h264e_vepu580.c774 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu580_prep()
778 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
782 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu580_prep()
H A Dhal_h264e_vepu510.c790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu510_prep()
798 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu510_prep()
H A Dhal_h264e_vepu511.c767 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu511_prep()
771 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu511_prep()
775 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu511_prep()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c830 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu540c_h265_set_pp_regs()
834 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu540c_h265_set_pp_regs()
838 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu540c_h265_set_pp_regs()
H A Dhal_h265e_vepu541.c1108 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff; in vepu541_h265_set_pp_regs()
1112 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff; in vepu541_h265_set_pp_regs()
1116 regs->src_udfv.wght_g2v = cfg_coeffs->_2v.g_coeff; in vepu541_h265_set_pp_regs()
H A Dhal_h265e_vepu510.c1476 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu510_h265_set_pp_regs()
1480 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu510_h265_set_pp_regs()
1484 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu510_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c2040 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu580_h265_set_pp_regs()
2044 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu580_h265_set_pp_regs()
2048 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu580_h265_set_pp_regs()