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Searched refs:csc_ofst_u (Results 1 – 21 of 21) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vepu511_reg.h129 RK_U32 csc_ofst_u : 8; member
H A Dhal_jpege_vepu540c_reg.h514 RK_U32 csc_ofst_u : 8; member
H A Dhal_jpege_vepu511.c279 regs->src_udfo.csc_ofst_u = 128; in vepu511_set_jpeg_reg()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu540c_common.c233 regs->reg0278_src_udfo.csc_ofst_u = 128; in vepu540c_set_jpeg_reg()
H A Dvepu540c_common.h621 RK_U32 csc_ofst_u : 8; member
H A Dvepu510_common.h594 RK_U32 csc_ofst_u : 8; member
H A Dvepu511_common.h923 RK_U32 csc_ofst_u : 8; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541_reg.h546 RK_U32 csc_ofst_u : 8; member
H A Dhal_h264e_vepu540c_reg.h433 RK_U32 csc_ofst_u : 8; member
H A Dhal_h264e_vepu541.c513 regs->reg021.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu541_prep()
531 regs->reg021.csc_ofst_u = cfg.offset[1]; in setup_vepu541_prep()
H A Dhal_h264e_vepu540c.c505 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu540c_prep()
523 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu540c_prep()
H A Dhal_h264e_vepu580.c786 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()
804 regs->reg_base.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu580_prep()
H A Dhal_h264e_vepu510.c802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu510_prep()
820 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu510_prep()
H A Dhal_h264e_vepu511.c779 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu511_prep()
797 reg_frm->common.src_udfo.csc_ofst_u = cfg.offset[1]; in setup_vepu511_prep()
H A Dhal_h264e_vepu580_reg.h408 RK_U32 csc_ofst_u : 8; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c_reg.h521 RK_U32 csc_ofst_u : 8; member
H A Dhal_h265e_vepu580_reg.h401 RK_U32 csc_ofst_u : 8; member
H A Dhal_h265e_vepu540c.c842 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu540c_h265_set_pp_regs()
H A Dhal_h265e_vepu510.c1488 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu510_h265_set_pp_regs()
H A Dhal_h265e_vepu511.c1211 reg_frm->common.src_udfo.csc_ofst_u = 128; in vepu511_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c2052 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu580_h265_set_pp_regs()