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Searched refs:_2y (Results 1 – 11 of 11) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.c29 ._2y = {.r_coeff = 66, .g_coeff = 129, .b_coeff = 25, .offset = 16},
36 ._2y = {.r_coeff = 47, .g_coeff = 157, .b_coeff = 16, .offset = 16},
46 ._2y = {.r_coeff = 77, .g_coeff = 150, .b_coeff = 29, .offset = 0},
53 ._2y = {.r_coeff = 54, .g_coeff = 183, .b_coeff = 18, .offset = 0},
H A Dvepu5xx_common.h92 VepuRgb2YuvCoeffs _2y; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c500 regs->reg018.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu541_prep()
501 regs->reg018.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu541_prep()
502 regs->reg018.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu541_prep()
512 regs->reg021.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu541_prep()
H A Dhal_h264e_vepu540c.c492 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu540c_prep()
493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
494 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu540c_prep()
504 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu540c_prep()
H A Dhal_h264e_vepu580.c773 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu580_prep()
774 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu580_prep()
775 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu580_prep()
785 regs->reg_base.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu580_prep()
H A Dhal_h264e_vepu510.c789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu510_prep()
801 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu510_prep()
H A Dhal_h264e_vepu511.c766 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu511_prep()
767 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu511_prep()
768 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu511_prep()
778 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in setup_vepu511_prep()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c829 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu540c_h265_set_pp_regs()
830 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu540c_h265_set_pp_regs()
831 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu540c_h265_set_pp_regs()
841 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu540c_h265_set_pp_regs()
H A Dhal_h265e_vepu541.c1107 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff; in vepu541_h265_set_pp_regs()
1108 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff; in vepu541_h265_set_pp_regs()
1109 regs->src_udfy.wght_b2y = cfg_coeffs->_2y.b_coeff; in vepu541_h265_set_pp_regs()
1119 regs->src_udfo.ofst_y = cfg_coeffs->_2y.offset; in vepu541_h265_set_pp_regs()
H A Dhal_h265e_vepu510.c1475 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu510_h265_set_pp_regs()
1476 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu510_h265_set_pp_regs()
1477 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu510_h265_set_pp_regs()
1487 reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu510_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c2039 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu580_h265_set_pp_regs()
2040 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu580_h265_set_pp_regs()
2041 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu580_h265_set_pp_regs()
2051 reg_base->reg0202_src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset; in vepu580_h265_set_pp_regs()