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/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dserial_scc.c78 volatile scc_uart_t *up; in mpc85xx_serial_init() local
86 up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); in mpc85xx_serial_init()
120 up->scc_genscc.scc_rbase = dpaddr; in mpc85xx_serial_init()
121 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); in mpc85xx_serial_init()
122 up->scc_genscc.scc_rfcr = CPMFCR_EB; in mpc85xx_serial_init()
123 up->scc_genscc.scc_tfcr = CPMFCR_EB; in mpc85xx_serial_init()
124 up->scc_genscc.scc_mrblr = 1; in mpc85xx_serial_init()
125 up->scc_maxidl = 0; in mpc85xx_serial_init()
126 up->scc_brkcr = 1; in mpc85xx_serial_init()
127 up->scc_parec = 0; in mpc85xx_serial_init()
[all …]
H A Dmp.c331 u32 up, cpu_up_mask, whoami; in plat_mp_up() local
352 up = ((1 << cpu_numcores()) - 1); in plat_mp_up()
354 bpcr |= (up << 24); in plat_mp_up()
367 if ((cpu_up_mask & up) == up) in plat_mp_up()
376 cpu_up_mask, up); in plat_mp_up()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drockchip-pinconf.dtsi7 pcfg_pull_up: pcfg-pull-up {
8 bias-pull-up;
99 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
100 bias-pull-up;
104 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
105 bias-pull-up;
109 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
110 bias-pull-up;
114 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
115 bias-pull-up;
[all …]
H A Dzynq-zc706.dts196 conf-pull-up {
198 bias-pull-up;
215 bias-pull-up;
242 bias-pull-up;
255 bias-pull-up;
H A Dzynq-zc702.dts49 linux,code = <103>; /* up */
277 conf-pull-up {
279 bias-pull-up;
296 bias-pull-up;
323 bias-pull-up;
336 bias-pull-up;
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_mpc8xx.c82 smc_uart_t __iomem *up; in smc_init() local
89 up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC]; in smc_init()
91 out_be16(&up->smc_rpbase, 0); in smc_init()
127 out_be16(&up->smc_rbase, CPM_SERIAL_BASE); in smc_init()
128 out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t)); in smc_init()
129 out_8(&up->smc_rfcr, SMC_EB); in smc_init()
130 out_8(&up->smc_tfcr, SMC_EB); in smc_init()
150 out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN); in smc_init()
151 out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE); in smc_init()
/rk3399_rockchip-uboot/arch/arm/mach-imx/
H A Dimx_bootaux.c46 int ret, up; in do_bootaux() local
51 up = arch_auxiliary_core_check_up(0); in do_bootaux()
52 if (up) { in do_bootaux()
/rk3399_rockchip-uboot/Documentation/devicetree/bindings/rtc/
H A Dbrcm,brcmstb-waketimer.txt1 Broadcom STB wake-up Timer
3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
4 ability to wake up the system from low-power suspend/standby modes.
/rk3399_rockchip-uboot/board/freescale/ls1021aiot/
H A Dls102xa_rcw_sd.cfg11 #SATA set-up
17 #HDMI set-up
/rk3399_rockchip-uboot/board/freescale/ls1021aqds/
H A DREADME15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
37 supporting speeds up to 1600Mtps
45 - Two PCI Express Gen2 controllers running at up to 5 GHz
59 - Four GPIO controllers supporting up to 109 general purpose I/O signals
65 - IPSec forwarding at up to 1Gbps
80 - Supports rates of up to 1600 MHz data-rate
/rk3399_rockchip-uboot/board/freescale/ls1021atwr/
H A DREADME15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
37 supporting speeds up to 1600Mtps
45 - Two PCI Express Gen2 controllers running at up to 5 GHz
59 - Four GPIO controllers supporting up to 109 general purpose I/O signals
65 - IPSec forwarding at up to 1Gbps
80 - Supports rates of up to 1600 MHz data-rate
/rk3399_rockchip-uboot/board/udoo/
H A DREADME20 - Insert the SD card in the board, power it up and U-Boot messages should
21 come up.
/rk3399_rockchip-uboot/board/solidrun/mx6cuboxi/
H A DREADME20 - Insert the SD card in the board, power it up and U-Boot messages should
21 come up.
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc67 - Cryptography acceleration (SEC) at up to 10 Gbps
68 - RegEx pattern matching acceleration (PME) at up to 10 Gbps
69 - Decompression/compression acceleration (DCE) at up to 20 Gbps
70 - Accelerated I/O processing (AIOP) at up to 20 Gbps
72 - 16 SerDes lanes at up to 10.3125 GHz
110 Support for up to 6 GBaud operation
194 - Cryptography acceleration (SEC) at up to 10 Gbps
195 - RegEx pattern matching acceleration (PME) at up to 10 Gbps
196 - Decompression/compression acceleration (DCE) at up to 20 Gbps
197 - Accelerated I/O processing (AIOP) at up to 20 Gbps
[all …]
/rk3399_rockchip-uboot/board/freescale/ls2080aqds/
H A DREADME25 chip-selects and two DIMM connectors. Support is up to 2133MT/s.
27 and two DIMM connectors. Support is up to 1600MT/s.
46 - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
47 - 8 MB high-speed flash Memory (up to 104 MHz)
48 - 512 MB low-speed flash Memory (up to 40 MHz)
53 - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
142 - Card can operate with up to 4 QSGMII lane simultaneously
143 - Card can operate with up to 8 SGMII lane simultaneously
/rk3399_rockchip-uboot/board/engicam/geam6ul/
H A DREADME27 - Insert the micro SD card in the board, power it up and U-Boot messages should
28 come up.
/rk3399_rockchip-uboot/board/freescale/ls1043ardb/
H A DREADME22 - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
30 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
33 - Two 4-pin serial ports at up to 115.2 Kbit/s
/rk3399_rockchip-uboot/board/engicam/isiotmx6ul/
H A DREADME27 - Insert the micro SD card in the board, power it up and U-Boot messages should
28 come up.
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx-spin-table9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
20 TLB. While booting, they set up another TLB in AS=1 space and jump into
/rk3399_rockchip-uboot/board/freescale/mx6ul_14x14_evk/
H A DREADME31 - Insert the micro SD card in the board, power it up and U-Boot messages should
32 come up.
/rk3399_rockchip-uboot/board/engicam/icorem6/
H A DREADME32 - Insert the micro SD card in the board, power it up and U-Boot messages should
33 come up.
/rk3399_rockchip-uboot/drivers/ram/
H A DKconfig7 tree. Generally some parameters are required to set up the RAM and
18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
/rk3399_rockchip-uboot/board/engicam/icorem6_rqs/
H A DREADME32 - Insert the micro SD card in the board, power it up and U-Boot messages should
33 come up.
/rk3399_rockchip-uboot/drivers/video/rk_eink/
H A Dtps65185.c259 static bool tps65185_hw_power_ack(struct tps65185_priv_data *priv_data, int up) in tps65185_hw_power_ack() argument
270 if (pg_status == 0xfa && up == 1) { in tps65185_hw_power_ack()
272 } else if (pg_status == 0x00 && up == 0) { in tps65185_hw_power_ack()
283 up ? "up" : "down", pg_status); in tps65185_hw_power_ack()
285 return (st == up); in tps65185_hw_power_ack()
/rk3399_rockchip-uboot/board/freescale/ls1046ardb/
H A DREADME27 - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
34 - DSPI: 64 MB high-speed flash Memory for boot code and storage (up to 108MHz)
37 - Two 4-pin serial ports at up to 115.2 Kbit/s

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