1*552a848eSStefano Babic /*
2*552a848eSStefano Babic * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*552a848eSStefano Babic *
4*552a848eSStefano Babic * SPDX-License-Identifier: GPL-2.0+
5*552a848eSStefano Babic */
6*552a848eSStefano Babic
7*552a848eSStefano Babic #include <common.h>
8*552a848eSStefano Babic #include <command.h>
9*552a848eSStefano Babic
10*552a848eSStefano Babic /* Allow for arch specific config before we boot */
__arch_auxiliary_core_up(u32 core_id,u32 boot_private_data)11*552a848eSStefano Babic static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
12*552a848eSStefano Babic {
13*552a848eSStefano Babic /* please define platform specific arch_auxiliary_core_up() */
14*552a848eSStefano Babic return CMD_RET_FAILURE;
15*552a848eSStefano Babic }
16*552a848eSStefano Babic
17*552a848eSStefano Babic int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
18*552a848eSStefano Babic __attribute__((weak, alias("__arch_auxiliary_core_up")));
19*552a848eSStefano Babic
20*552a848eSStefano Babic /* Allow for arch specific config before we boot */
__arch_auxiliary_core_check_up(u32 core_id)21*552a848eSStefano Babic static int __arch_auxiliary_core_check_up(u32 core_id)
22*552a848eSStefano Babic {
23*552a848eSStefano Babic /* please define platform specific arch_auxiliary_core_check_up() */
24*552a848eSStefano Babic return 0;
25*552a848eSStefano Babic }
26*552a848eSStefano Babic
27*552a848eSStefano Babic int arch_auxiliary_core_check_up(u32 core_id)
28*552a848eSStefano Babic __attribute__((weak, alias("__arch_auxiliary_core_check_up")));
29*552a848eSStefano Babic
30*552a848eSStefano Babic /*
31*552a848eSStefano Babic * To i.MX6SX and i.MX7D, the image supported by bootaux needs
32*552a848eSStefano Babic * the reset vector at the head for the image, with SP and PC
33*552a848eSStefano Babic * as the first two words.
34*552a848eSStefano Babic *
35*552a848eSStefano Babic * Per the cortex-M reference manual, the reset vector of M4 needs
36*552a848eSStefano Babic * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
37*552a848eSStefano Babic * of that vector. So to boot M4, the A core must build the M4's reset
38*552a848eSStefano Babic * vector with getting the PC and SP from image and filling them to
39*552a848eSStefano Babic * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
40*552a848eSStefano Babic * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
41*552a848eSStefano Babic * accessing the M4 TCMUL.
42*552a848eSStefano Babic */
do_bootaux(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])43*552a848eSStefano Babic int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
44*552a848eSStefano Babic {
45*552a848eSStefano Babic ulong addr;
46*552a848eSStefano Babic int ret, up;
47*552a848eSStefano Babic
48*552a848eSStefano Babic if (argc < 2)
49*552a848eSStefano Babic return CMD_RET_USAGE;
50*552a848eSStefano Babic
51*552a848eSStefano Babic up = arch_auxiliary_core_check_up(0);
52*552a848eSStefano Babic if (up) {
53*552a848eSStefano Babic printf("## Auxiliary core is already up\n");
54*552a848eSStefano Babic return CMD_RET_SUCCESS;
55*552a848eSStefano Babic }
56*552a848eSStefano Babic
57*552a848eSStefano Babic addr = simple_strtoul(argv[1], NULL, 16);
58*552a848eSStefano Babic
59*552a848eSStefano Babic printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
60*552a848eSStefano Babic
61*552a848eSStefano Babic ret = arch_auxiliary_core_up(0, addr);
62*552a848eSStefano Babic if (ret)
63*552a848eSStefano Babic return CMD_RET_FAILURE;
64*552a848eSStefano Babic
65*552a848eSStefano Babic return CMD_RET_SUCCESS;
66*552a848eSStefano Babic }
67*552a848eSStefano Babic
68*552a848eSStefano Babic U_BOOT_CMD(
69*552a848eSStefano Babic bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
70*552a848eSStefano Babic "Start auxiliary core",
71*552a848eSStefano Babic ""
72*552a848eSStefano Babic );
73