| /rk3399_rockchip-uboot/board/compulab/common/ |
| H A D | omap3_display.c | 271 static int parse_setting(char *setting) in parse_setting() argument
274 char *setting_start = setting; in parse_setting()
276 if (!strncmp(setting, "mode:", 5)) { in parse_setting()
277 return parse_mode(setting + 5); in parse_setting()
278 } else if (!strncmp(setting, "pixclock:", 9)) { in parse_setting()
279 return parse_pixclock(setting + 9); in parse_setting()
280 } else if (!strncmp(setting, "left:", 5)) { in parse_setting()
281 num_val = simple_strtoul(setting + 5, &setting, 0); in parse_setting()
283 } else if (!strncmp(setting, "right:", 6)) { in parse_setting()
284 num_val = simple_strtoul(setting + 6, &setting, 0); in parse_setting()
[all …]
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| /rk3399_rockchip-uboot/board/siemens/smartweb/ |
| H A D | smartweb.c | 243 struct sdramc_reg setting; in mem_init() local
245 setting.cr = SDRAM_BASE_CONF; in mem_init()
246 setting.mdr = AT91_SDRAMC_MD_SDRAM; in mem_init()
247 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; in mem_init()
257 sdramc_initialize(ATMEL_BASE_CS1, &setting); in mem_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rmobile/ |
| H A D | Kconfig.32 | 64 prompt "Qos setting primary"
71 Select normal mode for QoS setting.
76 Select multimedia primary mode for QoS setting.
81 Select GFX(graphics) primary mode for QoS setting.
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.marubun-pcmcia | 38 You should do the setting matched to your environment.
44 You should do the setting matched to your environment.
50 You should do the setting matched to your environment.
56 You should do the setting matched to your environment.
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| H A D | README.AMCC-eval-boards-cleanup | 14 the default setting. Option for environment in nvram is still available
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| /rk3399_rockchip-uboot/board/siemens/taurus/ |
| H A D | taurus.c | 165 struct sdramc_reg setting; in sdramc_configure() local
168 setting.cr = SDRAM_BASE_CONF | mask; in sdramc_configure()
169 setting.mdr = AT91_SDRAMC_MD_SDRAM; in sdramc_configure()
170 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; in sdramc_configure()
176 sdramc_initialize(ATMEL_BASE_CS1, &setting); in sdramc_configure()
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | socfpga_arria10_socdk_sdmmc_handoff.dtsi | 22 /* Bootloader setting: uboot.rbf_filename */
396 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
400 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
407 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
410 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
416 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
420 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
427 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
431 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
438 * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
[all …]
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| /rk3399_rockchip-uboot/board/freescale/mpc837xemds/ |
| H A D | README | 24 First, make sure the board default setting is consistent with the
25 document shipped with your board. Then apply the following setting:
26 SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
27 SW4[1-8]= 0000_0110 (core PLL setting)
30 SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/ |
| H A D | config.txt | 22 This setting will override any values configured via Kconfig.
29 if u-boot,mmc-env-offset* is present, this setting will take
41 device, specified in bytes. It is assumed that the setting
47 to override the CONFIG_SYS_SPI_U_BOOT_OFFS setting using a value
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| /rk3399_rockchip-uboot/drivers/pinctrl/ |
| H A D | pinctrl-at91.c | 210 u32 pin, u32 setting) in at91_mux_sama5d3_set_drivestrength() argument
219 if (!setting) in at91_mux_sama5d3_set_drivestrength()
223 set_drive_strength(reg, pin, setting); in at91_mux_sama5d3_set_drivestrength()
227 u32 pin, u32 setting) in at91_mux_sam9x5_set_drivestrength() argument
236 if (!setting) in at91_mux_sam9x5_set_drivestrength()
241 setting = DRIVE_STRENGTH_HI - setting; in at91_mux_sam9x5_set_drivestrength()
243 set_drive_strength(reg, pin, setting); in at91_mux_sam9x5_set_drivestrength()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-vf610/ |
| H A D | ddrmc-vf610.h | 66 u32 setting; member
71 u32 setting; member
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| /rk3399_rockchip-uboot/board/freescale/mpc832xemds/ |
| H A D | README | 26 First, make sure the board default setting is consistent with the document
27 shipped with your board. Then apply the following setting:
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
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| /rk3399_rockchip-uboot/board/freescale/p1022ds/ |
| H A D | README | 7 Pin Multiplex(hwconfig setting)
20 and AUDIO codec clock sources only setting as 11MHz or 12MHz !
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| /rk3399_rockchip-uboot/board/Barix/ipam390/ |
| H A D | ipam390-ais-uart.cfg | 17 ; This section allows setting the PLL0 system clock with a
32 ; This section allows setting up the PLL1. Usually this will
139 ; This section allows setting of a single PINMUX register.
140 ; This section can be included multiple times to allow setting
155 ; This section allows setting up the PLL1. Usually this will
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/ |
| H A D | ddrmc-vf610.c | 210 writel(cr_setting->setting, in ddrmc_ctrl_init_ddr3()
218 writel(phy_setting->setting, in ddrmc_ctrl_init_ddr3()
227 writel(phy_setting->setting, in ddrmc_ctrl_init_ddr3()
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| /rk3399_rockchip-uboot/board/freescale/t104xrdb/ |
| H A D | README | 285 NOR boot SW setting:
290 NAND boot SW setting:
295 SPI boot SW setting:
300 SD boot SW setting:
307 NOR boot SW setting:
312 NAND boot SW setting:
317 SPI boot SW setting:
322 SD boot SW setting:
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/video/ |
| H A D | exynos_mipi_dsi.txt | 26 samsung,dsim-config-p: P value for PMS setting.
27 samsung,dsim-config-m: M value for PMS setting.
28 samsung,dsim-config-s: S value for PMS setting.
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| /rk3399_rockchip-uboot/drivers/ram/ |
| H A D | Kconfig | 18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
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| /rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/ |
| H A D | README | 38 board by reading i2c bus and setting the appropriate mux values.
42 CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/i2c/ |
| H A D | i2c-gpio.txt | 16 The resulting transfer speed can be adjusted by setting the delay[us]
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| /rk3399_rockchip-uboot/board/toradex/colibri_imx6/ |
| H A D | Kconfig | 39 If executed on already fused modules it doesn't change any fuse setting.
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| /rk3399_rockchip-uboot/test/dm/ |
| H A D | regulator.c | 239 struct setting { struct
265 static const struct setting expected_setting_list[] = {
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| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen1.c | 12 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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| /rk3399_rockchip-uboot/drivers/clk/ |
| H A D | Kconfig | 20 setting up clocks within SPL, and allows the same drivers to be
30 setting up clocks within TPL, and allows the same drivers to be
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/regulator/ |
| H A D | regulator.txt | 40 The "regulator-name" constraint is used for setting the device's uclass
43 is chosen for setting the device's uclass platform data '.name' field.
|